arm: socfpga: set the mpuclk divider in the Altera group register

The mpuclk register in the Altera group of the clock manager
divides the mpu_clk that is generated from the C0 output of the main
pll.

Without this patch, the default value of the register is 1, so the mpuclk
will always get divided by 2 if the correct value is not set. For example,
on the Arria5 socdk board, the MPU clock is only 525 MHz, and it should be
1.05 GHz.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

1 files changed, 3 insertions, 0 deletions

diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c
index aa71636..29e18f8 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -167,6 +167,9 @@ void cm_basic_init(const struct cm_config * const cfg)
 	/* main mpu */
 	writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk);
 
+	/* altera group mpuclk */
+	writel(cfg->altera_grp_mpuclk, &clock_manager_base->altera.mpuclk);
+
 	/* main main clock */
 	writel(cfg->mainclk, &clock_manager_base->main_pll.mainclk);