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authorLey Foon Tan <ley.foon.tan@intel.com>2017-04-25 18:44:37 (GMT)
committerMarek Vasut <marex@denx.de>2017-05-18 09:33:17 (GMT)
commitd83b8193ad0378c389adb0db162eab13cd5bd9b5 (patch)
tree25973482bbd80f336f31df2e4d08a9a31d3c8883 /arch/arm/mach-socfpga
parentd1c559af5fb1a513eef1adf37713659d4e4e1968 (diff)
downloadu-boot-d83b8193ad0378c389adb0db162eab13cd5bd9b5.tar.xz
arm: socfpga: Add A10 macros
Add i2c, timer and other A10 macros. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Diffstat (limited to 'arch/arm/mach-socfpga')
-rw-r--r--arch/arm/mach-socfpga/include/mach/base_addr_a10.h8
1 files changed, 7 insertions, 1 deletions
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
index a7056d4..7818aa5 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2014 Altera Corporation <www.altera.com>
+ * Copyright (C) 2014-2017 Altera Corporation <www.altera.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -29,17 +29,23 @@
#define SOCFPGA_MPUL2_ADDRESS 0xfffff000
#define SOCFPGA_I2C0_ADDRESS 0xffc02200
#define SOCFPGA_I2C1_ADDRESS 0xffc02300
+#define SOCFPGA_I2C2_ADDRESS 0xffc02400
+#define SOCFPGA_I2C3_ADDRESS 0xffc02500
+#define SOCFPGA_I2C4_ADDRESS 0xffc02600
#define SOCFPGA_ECC_OCRAM_ADDRESS 0xff8c3000
#define SOCFPGA_UART0_ADDRESS 0xffc02000
#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000
+#define SOCFPGA_OSC1TIMER1_ADDRESS 0xffd00100
#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
#define SOCFPGA_SDR_ADDRESS 0xffcfb000
+#define SOCFPGA_NOC_L4_PRIV_FLT_OFST 0xffd11000
#define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xffd12400
#define SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS 0xffd13200
#define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS 0xffd13300
#define SOCFPGA_SDR_FIREWALL_L3_ADDRESS 0xffd13400
+#define SOCFPGA_NOC_FW_H2F_SCR_OFST 0xffd13500
#endif /* _SOCFPGA_A10_BASE_HARDWARE_H_ */