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authorThierry Reding <treding@nvidia.com>2015-09-08 09:38:04 (GMT)
committerTom Warren <twarren@nvidia.com>2015-09-16 23:11:31 (GMT)
commit8e1601d994e2fa8b8c7826470c3d923a684492a4 (patch)
treebe4bc580ea0ce2f4005efbf1f54a5f346e5c8c21 /arch/arm/mach-tegra/cmd_enterrcm.c
parentaba11d4476b56eb7712184597eb303ae544f0c69 (diff)
downloadu-boot-8e1601d994e2fa8b8c7826470c3d923a684492a4.tar.xz
ARM: tegra114: Clear IDDQ when enabling PLLC
Enabling a PLL while IDDQ is high. The Linux kernel checks for this condition and warns about it verbosely, so while this seems to work fine, fix it up according to the programming guidelines provided in the Tegra K1 TRM (v02p), Section 5.3.8.1 ("PLLC and PLLC4 Startup Sequence"). The Tegra114 TRM doesn't contain this information, but the programming of PLLC is the same on Tegra114 and Tegra124. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
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