diff options
| author | Stephen Warren <swarren@nvidia.com> | 2016-10-10 15:50:55 (GMT) |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2016-10-10 18:00:03 (GMT) |
| commit | d40d69ee350b62af90c2b522e05cbb3eb5f27112 (patch) | |
| tree | 9f4a2356c46bdd04335e8272da214ed91b6662e8 /arch/arm/mach-tegra | |
| parent | d5a24d8b53d350364bd429b7104ec369b817e4b8 (diff) | |
| download | u-boot-d40d69ee350b62af90c2b522e05cbb3eb5f27112.tar.xz | |
ARM: tegra: reduce DRAM size mapped into MMU on ARM64
ARM CPUs can architecturally (speculatively) prefetch completely arbitrary
normal memory locations, as defined by the current translation tables. The
current MMU configuration for 64-bit Tegras maps an extremely large range
of addresses as DRAM, well beyond the actual physical maximum DRAM window,
even though U-Boot only needs access to the first 2GB of DRAM; the Tegra
port of U-Boot deliberately limits itself to 2GB of RAM since some HW
modules on at least some 64-bit Tegra SoCs can only access a 32-bit
physical address space. This change reduces the amount of RAM mapped via
the MMU to disallow the CPU from ever speculatively accessing RAM that
U-Boot will definitely not access. This avoids the possibility of the HW
raising SError due to accesses to always-invalid physical addresses.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra')
| -rw-r--r-- | arch/arm/mach-tegra/arm64-mmu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/arm64-mmu.c b/arch/arm/mach-tegra/arm64-mmu.c index 7b1d258..a79a519 100644 --- a/arch/arm/mach-tegra/arm64-mmu.c +++ b/arch/arm/mach-tegra/arm64-mmu.c @@ -23,7 +23,7 @@ static struct mm_region tegra_mem_map[] = { }, { .virt = 0x80000000UL, .phys = 0x80000000UL, - .size = 0xff80000000UL, + .size = 0x80000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { |