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authorMasahiro Yamada <yamada.masahiro@socionext.com>2016-08-10 07:08:46 (GMT)
committerMasahiro Yamada <yamada.masahiro@socionext.com>2016-08-11 08:49:44 (GMT)
commit8fca073271706f3d856c6554c2b5400ac9c83c10 (patch)
tree06c882eb921d1931b3fea21dbd0ec81fd3452f86 /arch/arm/mach-uniphier/arm32/cache-uniphier.h
parent7382d1782648e6e8e5be878e9b9a3cbfd1912001 (diff)
downloadu-boot-8fca073271706f3d856c6554c2b5400ac9c83c10.tar.xz
ARM: uniphier: fix CONFIG_SYS_CACHELINE_SIZE when outer cache is on
The UniPhier outer cache (L2 cache on ARMv7 SoCs) has 128 byte line length and its tags are also managed per 128 byte line. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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