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| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-08-10 07:08:37 (GMT) |
|---|---|---|
| committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-08-11 08:49:11 (GMT) |
| commit | 95a1feca2e852ade552495e3688c5ef2afae68aa (patch) | |
| tree | fafdb6f16d0c9e19035b00efb507f8516eb7d81e /arch/arm/mach-uniphier/arm32/cache-uniphier.h | |
| parent | 3ffc7475747e455c937339ab7c935af8e5edb2d1 (diff) | |
| download | u-boot-95a1feca2e852ade552495e3688c5ef2afae68aa.tar.xz | |
ARM: uniphier: support prefetch and touch operations for outer cache
The UniPhier outer cache (L2 cache on ARMv7 SoCs) can be used as
SRAM by locking ways.
These functions will be used to transfer the trampoline code for SMP
into the locked SRAM.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm/mach-uniphier/arm32/cache-uniphier.h')
| -rw-r--r-- | arch/arm/mach-uniphier/arm32/cache-uniphier.h | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/arm/mach-uniphier/arm32/cache-uniphier.h b/arch/arm/mach-uniphier/arm32/cache-uniphier.h new file mode 100644 index 0000000..f67f6ae --- /dev/null +++ b/arch/arm/mach-uniphier/arm32/cache-uniphier.h @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CACHE_UNIPHIER_H +#define __CACHE_UNIPHIER_H + +#include <linux/types.h> + +void uniphier_cache_prefetch_range(u32 start, u32 end, u32 ways); +void uniphier_cache_touch_range(u32 start, u32 end, u32 ways); +void uniphier_cache_touch_zero_range(u32 start, u32 end, u32 ways); + +#endif /* __CACHE_UNIPHIER_H */ |