ARM: uniphier: add PLL init code for LD11 SoC

 - Initialize PLLs (SPL initializes only DPLL to save the precious
   SPL memory footprint)
 - Adjust CPLL/MPLL to the final tape-out frequency
 - Set the Cortex-A53 clock to the maximum frequency since it is
   running at 500MHz (SPLL/4) on startup

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

1 files changed, 3 insertions, 2 deletions

diff --git a/arch/arm/mach-uniphier/clk/Makefile b/arch/arm/mach-uniphier/clk/Makefile
index c8d59ea..95f433e 100644
--- a/arch/arm/mach-uniphier/clk/Makefile
+++ b/arch/arm/mach-uniphier/clk/Makefile
@@ -11,7 +11,7 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= early-clk-ld4.o dpll-sld8.o
 obj-$(CONFIG_ARCH_UNIPHIER_PRO5)	+= early-clk-pro5.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= early-clk-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= early-clk-pxs2.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD11)	+= early-clk-ld11.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD11)	+= early-clk-ld11.o dpll-ld11.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= early-clk-ld20.o dpll-ld20.o
 
 else
@@ -23,9 +23,10 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= clk-ld4.o pll-ld4.o dpll-tail.o
 obj-$(CONFIG_ARCH_UNIPHIER_PRO5)	+= clk-pro5.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= clk-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= clk-pxs2.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD11)	+= clk-ld11.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD11)	+= clk-ld11.o pll-ld11.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= clk-ld20.o pll-ld20.o
 
 endif
 
+obj-$(CONFIG_ARCH_UNIPHIER_LD11)	+= pll-base-ld20.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= pll-base-ld20.o