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author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2017-01-15 05:59:03 (GMT) |
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committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2017-01-17 00:00:40 (GMT) |
commit | 78c627cf1f808d5ae9240809a81b71903bdf4fe2 (patch) | |
tree | 9193f6e6389c787efbea9b60ef9a567a09600a2e /arch/arm/mach-uniphier/clk/clk-dram-ld20.c | |
parent | a314a245d14547df0a88e1ea568116fd7947daf4 (diff) | |
download | u-boot-78c627cf1f808d5ae9240809a81b71903bdf4fe2.tar.xz |
ARM: uniphier: split out UMC clock enable
The clock enable bits for UMC are more SoC-specific than for
the other hardware blocks. Separate the UMC clocks and the other
clocks for better code reuse across SoCs.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm/mach-uniphier/clk/clk-dram-ld20.c')
-rw-r--r-- | arch/arm/mach-uniphier/clk/clk-dram-ld20.c | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/arch/arm/mach-uniphier/clk/clk-dram-ld20.c b/arch/arm/mach-uniphier/clk/clk-dram-ld20.c new file mode 100644 index 0000000..62e5acd --- /dev/null +++ b/arch/arm/mach-uniphier/clk/clk-dram-ld20.c @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2016-2017 Socionext Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <linux/io.h> + +#include "../init.h" +#include "../sc64-regs.h" + +void uniphier_ld20_dram_clk_init(void) +{ + u32 tmp; + + /* deassert reset */ + tmp = readl(SC_RSTCTRL7); + tmp |= SC_RSTCTRL7_UMCSB | SC_RSTCTRL7_UMCA2 | SC_RSTCTRL7_UMCA1 | + SC_RSTCTRL7_UMCA0 | SC_RSTCTRL7_UMC32 | SC_RSTCTRL7_UMC31 | + SC_RSTCTRL7_UMC30; + writel(tmp, SC_RSTCTRL7); + + /* provide clocks */ + tmp = readl(SC_CLKCTRL7); + tmp |= SC_CLKCTRL7_UMCSB | SC_CLKCTRL7_UMC32 | SC_CLKCTRL7_UMC31 | + SC_CLKCTRL7_UMC30; + writel(tmp, SC_CLKCTRL7); +} |