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author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2015-09-21 15:27:39 (GMT) |
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committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2015-09-24 15:58:38 (GMT) |
commit | 323d1f9d5bebfe55e97e23c8094055685665afef (patch) | |
tree | 4fe6b5ffd3aab68a945de9750d145514271d2321 /arch/arm/mach-uniphier/ph1-pro4/clkrst_init.c | |
parent | 5451b777de392043c03626f6cbbc3940c49c3417 (diff) | |
download | u-boot-323d1f9d5bebfe55e97e23c8094055685665afef.tar.xz |
ARM: uniphier: allow to enable multiple SoCs
Before this commit, the Kconfig menu in mach-uniphier only allowed us
to choose one SoC to be compiled. Each SoC has its own defconfig file
for the build-test coverage. Consequently, some defconfig files are
duplicated with only the difference in CONFIG_DEFAULT_DEVICE_TREE and
CONFIG_{SOC_NAME}=y.
Now, most of board-specific parameters have been moved to device trees,
so it makes sense to include init code of multiple SoCs into a single
image as long as the SoCs have similar architecture. In fact, some
SoCs of UniPhier family are very similar:
- PH1-LD4 and PH1-sLD8
- PH1-LD6b and ProXstream2 (will be added in the upcoming commit)
This commit will be helpful to merge some defconfig files for better
maintainability.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm/mach-uniphier/ph1-pro4/clkrst_init.c')
-rw-r--r-- | arch/arm/mach-uniphier/ph1-pro4/clkrst_init.c | 56 |
1 files changed, 0 insertions, 56 deletions
diff --git a/arch/arm/mach-uniphier/ph1-pro4/clkrst_init.c b/arch/arm/mach-uniphier/ph1-pro4/clkrst_init.c deleted file mode 100644 index 46cace7..0000000 --- a/arch/arm/mach-uniphier/ph1-pro4/clkrst_init.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <linux/io.h> -#include <mach/sc-regs.h> - -void clkrst_init(void) -{ - u32 tmp; - - /* deassert reset */ - tmp = readl(SC_RSTCTRL); -#ifdef CONFIG_USB_XHCI_UNIPHIER - tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_USB3C0 | - SC_RSTCTRL_NRST_GIO; -#endif -#ifdef CONFIG_UNIPHIER_ETH - tmp |= SC_RSTCTRL_NRST_ETHER; -#endif -#ifdef CONFIG_USB_EHCI_UNIPHIER - tmp |= SC_RSTCTRL_NRST_STDMAC; -#endif -#ifdef CONFIG_NAND_DENALI - tmp |= SC_RSTCTRL_NRST_NAND; -#endif - writel(tmp, SC_RSTCTRL); - readl(SC_RSTCTRL); /* dummy read */ - -#ifdef CONFIG_USB_XHCI_UNIPHIER - tmp = readl(SC_RSTCTRL2); - tmp |= SC_RSTCTRL2_NRST_USB3B1 | SC_RSTCTRL2_NRST_USB3C1; - writel(tmp, SC_RSTCTRL2); - readl(SC_RSTCTRL2); /* dummy read */ -#endif - - /* privide clocks */ - tmp = readl(SC_CLKCTRL); -#ifdef CONFIG_USB_XHCI_UNIPHIER - tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 | - SC_CLKCTRL_CEN_GIO; -#endif -#ifdef CONFIG_UNIPHIER_ETH - tmp |= SC_CLKCTRL_CEN_ETHER; -#endif -#ifdef CONFIG_USB_EHCI_UNIPHIER - tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC; -#endif -#ifdef CONFIG_NAND_DENALI - tmp |= SC_CLKCTRL_CEN_NAND; -#endif - writel(tmp, SC_CLKCTRL); - readl(SC_CLKCTRL); /* dummy read */ -} |