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authorMasahiro Yamada <yamada.masahiro@socionext.com>2015-09-21 15:27:36 (GMT)
committerMasahiro Yamada <yamada.masahiro@socionext.com>2015-09-24 15:27:53 (GMT)
commitfcbcd59730255018dbe78af9294598273a85a0de (patch)
tree6ca5a91bea033ed8545fa9566d765627bdb266ab /arch/arm/mach-uniphier/ph1-sld3
parent257b11f32d0ba451b8b7eba72f0db5e182d425dd (diff)
downloadu-boot-fcbcd59730255018dbe78af9294598273a85a0de.tar.xz
ARM: uniphier: fix glitch signal problem for low-level debug
Currently, IECTRL is enabled after pin-mux settings for the low-level debugging for PH1-LD4 and PH1-sLD8. While IECTRL is disabled, input signals are pulled-down, i.e. glitch signal (Low to High transition) problem occurs if pin-mux is set up first. As a result, one invalid character is input to the UART block and the auto-boot counting is terminated immediately. The correct initialization procedure is: [1] Enable IECTRL (if IECTRL exists for the pins) [2] Set up pin-muxing [3] Deassert the reset of the hardware block Currently, the low-level debugging is working for PH1-sLD3 and PH1-Pro4, but just in case, follow the sequence for all the SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm/mach-uniphier/ph1-sld3')
-rw-r--r--arch/arm/mach-uniphier/ph1-sld3/lowlevel_debug.S6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/mach-uniphier/ph1-sld3/lowlevel_debug.S b/arch/arm/mach-uniphier/ph1-sld3/lowlevel_debug.S
index ee2eae6..f4eccb4 100644
--- a/arch/arm/mach-uniphier/ph1-sld3/lowlevel_debug.S
+++ b/arch/arm/mach-uniphier/ph1-sld3/lowlevel_debug.S
@@ -15,6 +15,9 @@
#include <mach/debug-uart.S>
ENTRY(setup_lowlevel_debug)
+ sg_set_pinsel 63, 0, 4, 4, r0, r1
+ sg_set_pinsel 64, 1, 4, 4, r0, r1
+
ldr r0, =BCSCR5
ldr r1, =0x24440000
str r1, [r0]
@@ -26,8 +29,5 @@ ENTRY(setup_lowlevel_debug)
init_debug_uart r0, r1, r2
- sg_set_pinsel 63, 0, 4, 4, r0, r1
- sg_set_pinsel 64, 1, 4, 4, r0, r1
-
mov pc, lr
ENDPROC(setup_lowlevel_debug)