diff options
author | Vitaly Andrianov <vitalya@ti.com> | 2015-09-19 10:56:40 (GMT) |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2015-10-22 18:22:15 (GMT) |
commit | bda920c65e7cc299e6ef0dc6e676fe672609ce12 (patch) | |
tree | 62ea0859242e5188851daaf365c843eefb495157 /arch/arm | |
parent | f9c4a51c3e1bc73c5c2ae178cf41aa85bada1fc8 (diff) | |
download | u-boot-bda920c65e7cc299e6ef0dc6e676fe672609ce12.tar.xz |
ARM: k2g: Add pll data
Add pll data for k2g
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/mach-keystone/clock.c | 5 | ||||
-rw-r--r-- | arch/arm/mach-keystone/include/mach/clock-k2g.h | 18 | ||||
-rw-r--r-- | arch/arm/mach-keystone/include/mach/clock.h | 6 | ||||
-rw-r--r-- | arch/arm/mach-keystone/include/mach/hardware.h | 2 |
4 files changed, 31 insertions, 0 deletions
diff --git a/arch/arm/mach-keystone/clock.c b/arch/arm/mach-keystone/clock.c index 6cb6467..d936896 100644 --- a/arch/arm/mach-keystone/clock.c +++ b/arch/arm/mach-keystone/clock.c @@ -31,6 +31,7 @@ const struct keystone_pll_regs keystone_pll_regs[] = { [TETRIS_PLL] = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1}, [DDR3A_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1}, [DDR3B_PLL] = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1}, + [UART_PLL] = {KS2_UARTPLLCTL0, KS2_UARTPLLCTL1}, }; inline void pll_pa_clk_sel(void) @@ -313,6 +314,10 @@ static unsigned long pll_freq_get(int pll) ret = external_clk[ddr3b_clk]; reg = KS2_DDR3BPLLCTL0; break; + case UART_PLL: + ret = external_clk[uart_clk]; + reg = KS2_UARTPLLCTL0; + break; default: return 0; } diff --git a/arch/arm/mach-keystone/include/mach/clock-k2g.h b/arch/arm/mach-keystone/include/mach/clock-k2g.h new file mode 100644 index 0000000..4d3f92e --- /dev/null +++ b/arch/arm/mach-keystone/include/mach/clock-k2g.h @@ -0,0 +1,18 @@ +/* + * K2G: Clock data + * + * (C) Copyright 2015 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_CLOCK_K2G_H +#define __ASM_ARCH_CLOCK_K2G_H + +#define PLLSET_CMD_LIST "<pa|arm|ddr3>" + +#define DEV_SUPPORTED_SPEEDS 0xfff +#define ARM_SUPPORTED_SPEEDS 0xfff + +#endif diff --git a/arch/arm/mach-keystone/include/mach/clock.h b/arch/arm/mach-keystone/include/mach/clock.h index 7e51702..3d2e2a2 100644 --- a/arch/arm/mach-keystone/include/mach/clock.h +++ b/arch/arm/mach-keystone/include/mach/clock.h @@ -24,8 +24,13 @@ #include <asm/arch/clock-k2l.h> #endif +#ifdef CONFIG_SOC_K2G +#include <asm/arch/clock-k2g.h> +#endif + #define CORE_PLL MAIN_PLL #define DDR3_PLL DDR3A_PLL +#define NSS_PLL PASS_PLL #define CLK_LIST(CLK)\ CLK(0, core_pll_clk)\ @@ -75,6 +80,7 @@ enum { PASS_PLL, DDR3A_PLL, DDR3B_PLL, + UART_PLL, MAX_PLL_COUNT, }; diff --git a/arch/arm/mach-keystone/include/mach/hardware.h b/arch/arm/mach-keystone/include/mach/hardware.h index cbb836c..2c5167e 100644 --- a/arch/arm/mach-keystone/include/mach/hardware.h +++ b/arch/arm/mach-keystone/include/mach/hardware.h @@ -167,6 +167,8 @@ typedef volatile unsigned int *dv_reg_p; #define KS2_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C) #define KS2_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370) #define KS2_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374) +#define KS2_UARTPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x390) +#define KS2_UARTPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x394) #define KS2_PLL_CNTRL_BASE 0x02310000 #define KS2_CLOCK_BASE KS2_PLL_CNTRL_BASE |