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author | Tom Rini <trini@konsulko.com> | 2016-12-05 22:00:23 (GMT) |
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committer | Tom Rini <trini@konsulko.com> | 2016-12-05 22:00:23 (GMT) |
commit | bf50ac918bfbc0042e43b0a5c87cfa9dd4351e0a (patch) | |
tree | dd4473fe2bfce799aac320280f64c22b3e891a4a /arch/arm | |
parent | 0bf1bc44070723f032ffac650eeff5157a289206 (diff) | |
parent | dd2ad2f1318975da1cf64cf95a4a3b3ed44172a5 (diff) | |
download | u-boot-bf50ac918bfbc0042e43b0a5c87cfa9dd4351e0a.tar.xz |
Merge git://git.denx.de/u-boot-fsl-qoriq
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 7 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 7 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c | 1 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/soc.c | 42 | ||||
-rw-r--r-- | arch/arm/dts/ls1021a.dtsi | 1 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 1 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 |
7 files changed, 59 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index ed1c4ee..6772584 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -76,6 +76,13 @@ config SECURE_BOOT help Enable Freescale Secure Boot feature +config QSPI_AHB_INIT + bool "Init the QSPI AHB bus" + help + The default setting for QSPI AHB bus just support 3bytes addressing. + But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB + bus for those flashes to support the full QSPI flash size. + config SYS_FSL_IFC_BANK_COUNT int "Maximum banks of Integrated flash controller" depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index d6ee546..ffbbd72 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -26,6 +26,9 @@ #ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT #include <asm/armv8/sec_firmware.h> #endif +#ifdef CONFIG_SYS_FSL_DDR +#include <fsl_ddr.h> +#endif DECLARE_GLOBAL_DATA_PTR; @@ -403,7 +406,9 @@ int arch_early_init_r(void) #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 erratum_a009635(); #endif - +#if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR) + erratum_a009942_check_cpo(); +#endif #ifdef CONFIG_MP #if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && defined(CONFIG_ARMV8_PSCI) /* Check the psci version to determine if the psci is supported */ diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c index 67d605e..ab83e85 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c @@ -36,6 +36,7 @@ static struct serdes_config serdes1_cfg_tbl[] = { {0x35, {QSGMII_D, QSGMII_C, QSGMII_B, PCIE2, XFI4, XFI3, XFI2, XFI1 } }, {0x39, {SGMII8, SGMII7, SGMII6, PCIE2, SGMII4, SGMII3, SGMII2, PCIE1 } }, + {0x3B, {XFI8, XFI7, XFI6, PCIE2, XFI4, XFI3, XFI2, PCIE1 } }, {0x4B, {PCIE2, PCIE2, PCIE2, PCIE2, XFI4, XFI3, XFI2, XFI1 } }, {0x4C, {XFI8, XFI7, XFI6, XFI5, PCIE1, PCIE1, PCIE1, PCIE1 } }, {0x4D, {SGMII8, SGMII7, PCIE2, PCIE2, SGMII4, SGMII3, PCIE1, PCIE1 } }, diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 6c42387..2f54625 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -373,6 +373,45 @@ void fsl_lsch2_early_init_f(void) } #endif +#ifdef CONFIG_QSPI_AHB_INIT +/* Enable 4bytes address support and fast read */ +int qspi_ahb_init(void) +{ + u32 *qspi_lut, lut_key, *qspi_key; + + qspi_key = (void *)SYS_FSL_QSPI_ADDR + 0x300; + qspi_lut = (void *)SYS_FSL_QSPI_ADDR + 0x310; + + lut_key = in_be32(qspi_key); + + if (lut_key == 0x5af05af0) { + /* That means the register is BE */ + out_be32(qspi_key, 0x5af05af0); + /* Unlock the lut table */ + out_be32(qspi_key + 1, 0x00000002); + out_be32(qspi_lut, 0x0820040c); + out_be32(qspi_lut + 1, 0x1c080c08); + out_be32(qspi_lut + 2, 0x00002400); + /* Lock the lut table */ + out_be32(qspi_key, 0x5af05af0); + out_be32(qspi_key + 1, 0x00000001); + } else { + /* That means the register is LE */ + out_le32(qspi_key, 0x5af05af0); + /* Unlock the lut table */ + out_le32(qspi_key + 1, 0x00000002); + out_le32(qspi_lut, 0x0820040c); + out_le32(qspi_lut + 1, 0x1c080c08); + out_le32(qspi_lut + 2, 0x00002400); + /* Lock the lut table */ + out_le32(qspi_key, 0x5af05af0); + out_le32(qspi_key + 1, 0x00000001); + } + + return 0; +} +#endif + #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { @@ -382,6 +421,9 @@ int board_late_init(void) #ifdef CONFIG_CHAIN_OF_TRUST fsl_setenv_chain_of_trust(); #endif +#ifdef CONFIG_QSPI_AHB_INIT + qspi_ahb_init(); +#endif return 0; } diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi index 119b1af..37be169 100644 --- a/arch/arm/dts/ls1021a.dtsi +++ b/arch/arm/dts/ls1021a.dtsi @@ -176,6 +176,7 @@ #size-cells = <0>; reg = <0x1550000 0x10000>, <0x40000000 0x4000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; num-cs = <2>; big-endian; status = "disabled"; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index d684a07..b3cfd89 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -18,6 +18,7 @@ #define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000) #define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x00400000) #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) +#define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000) #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000) #define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000) #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 2df56f7..e18dcbd 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -19,6 +19,7 @@ #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000) #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000) #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000) +#define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x010c0000) #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000) #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000) #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500) |