diff options
author | Mike Frysinger <vapier@gentoo.org> | 2010-12-17 20:25:09 (GMT) |
---|---|---|
committer | Mike Frysinger <vapier@gentoo.org> | 2011-04-08 04:44:26 (GMT) |
commit | cca07417d594fcae589463d1678d639810f986cd (patch) | |
tree | 77dcd48e8acc00b5a5003f68a9c47067c7aca083 /arch/blackfin/cpu | |
parent | 5a9a2c55d14260bc5b9fb6c36e2b32ee325a8aec (diff) | |
download | u-boot-cca07417d594fcae589463d1678d639810f986cd.tar.xz |
Blackfin: BF50x: new processor port
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/cpu')
-rw-r--r-- | arch/blackfin/cpu/gpio.c | 8 | ||||
-rw-r--r-- | arch/blackfin/cpu/initcode.c | 25 | ||||
-rw-r--r-- | arch/blackfin/cpu/serial.h | 21 |
3 files changed, 37 insertions, 17 deletions
diff --git a/arch/blackfin/cpu/gpio.c b/arch/blackfin/cpu/gpio.c index 488ca11..cb96721 100644 --- a/arch/blackfin/cpu/gpio.c +++ b/arch/blackfin/cpu/gpio.c @@ -45,7 +45,7 @@ static struct gpio_port_t * const gpio_array[] = { #if defined(BF533_FAMILY) (struct gpio_port_t *) FIO_FLAG_D, #elif defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x) \ - || defined(BF538_FAMILY) + || defined(BF538_FAMILY) || defined(CONFIG_BF50x) (struct gpio_port_t *) PORTFIO, # if !defined(BF538_FAMILY) (struct gpio_port_t *) PORTGIO, @@ -71,7 +71,8 @@ static struct gpio_port_t * const gpio_array[] = { #endif }; -#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x) +#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x) || \ + defined(CONFIG_BF50x) static unsigned short * const port_fer[] = { (unsigned short *) PORTF_FER, (unsigned short *) PORTG_FER, @@ -202,7 +203,8 @@ static void port_setup(unsigned gpio, unsigned short usage) if (check_gpio(gpio)) return; -#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x) +#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x) || \ + defined(CONFIG_BF50x) if (usage == GPIO_USAGE) *port_fer[gpio_bank(gpio)] &= ~gpio_bit(gpio); else diff --git a/arch/blackfin/cpu/initcode.c b/arch/blackfin/cpu/initcode.c index 433d477..750add0 100644 --- a/arch/blackfin/cpu/initcode.c +++ b/arch/blackfin/cpu/initcode.c @@ -341,13 +341,13 @@ maybe_self_refresh(ADI_BOOT_DATA *bs) return false; /* If external memory is enabled, put it into self refresh first. */ -#ifdef EBIU_RSTCTL +#if defined(EBIU_RSTCTL) if (bfin_read_EBIU_RSTCTL() & DDR_SRESET) { serial_putc('b'); bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | SRREQ); return true; } -#else +#elif defined(EBIU_SDGCTL) if (bfin_read_EBIU_SDBCTL() & EBE) { serial_putc('b'); bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS); @@ -373,12 +373,15 @@ program_clocks(ADI_BOOT_DATA *bs, bool put_into_srfs) /* If we're entering self refresh, make sure it has happened. */ if (put_into_srfs) -#ifdef EBIU_RSTCTL +#if defined(EBIU_RSTCTL) while (!(bfin_read_EBIU_RSTCTL() & SRACK)) -#else + continue; +#elif defined(EBIU_SDGCTL) while (!(bfin_read_EBIU_SDSTAT() & SDSRA)) -#endif continue; +#else + ; +#endif serial_putc('c'); @@ -536,7 +539,7 @@ program_memory_controller(ADI_BOOT_DATA *bs, bool put_into_srfs) /* Program the external memory controller before we come out of * self-refresh. This only works with our SDRAM controller. */ -#ifndef EBIU_RSTCTL +#ifdef EBIU_SDGCTL # ifdef CONFIG_EBIU_SDRRC_VAL bfin_write_EBIU_SDRRC(CONFIG_EBIU_SDRRC_VAL); # endif @@ -552,9 +555,9 @@ program_memory_controller(ADI_BOOT_DATA *bs, bool put_into_srfs) /* Now that we've reprogrammed, take things out of self refresh. */ if (put_into_srfs) -#ifdef EBIU_RSTCTL +#if defined(EBIU_RSTCTL) bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ)); -#else +#elif defined(EBIU_SDGCTL) bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() & ~(SRFS)); #endif @@ -646,10 +649,10 @@ program_async_controller(ADI_BOOT_DATA *bs) serial_putc('b'); /* Not all parts have these additional MMRs. */ -#ifdef EBIU_MODE -# ifdef CONFIG_EBIU_MBSCTL_VAL +#ifdef EBIU_MBSCTL bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTL_VAL); -# endif +#endif +#ifdef EBIU_MODE # ifdef CONFIG_EBIU_MODE_VAL bfin_write_EBIU_MODE(CONFIG_EBIU_MODE_VAL); # endif diff --git a/arch/blackfin/cpu/serial.h b/arch/blackfin/cpu/serial.h index b0cf09a..7999a19 100644 --- a/arch/blackfin/cpu/serial.h +++ b/arch/blackfin/cpu/serial.h @@ -31,13 +31,19 @@ #define LOB(x) ((x) & 0xFF) #define HIB(x) (((x) >> 8) & 0xFF) +#if defined(__ADSPBF50x__) || defined(__ADSPBF54x__) +# define BFIN_UART_HW_VER 2 +#else +# define BFIN_UART_HW_VER 1 +#endif + /* * All Blackfin system MMRs are padded to 32bits even if the register * itself is only 16bits. So use a helper macro to streamline this. */ #define __BFP(m) u16 m; u16 __pad_##m struct bfin_mmr_serial { -#ifdef __ADSPBF54x__ +#if BFIN_UART_HW_VER == 2 __BFP(dll); __BFP(dlh); __BFP(gctl); @@ -88,7 +94,7 @@ struct bfin_mmr_serial { #endif #define pUART ((volatile struct bfin_mmr_serial *)UART_DLL) -#ifdef __ADSPBF54x__ +#if BFIN_UART_HW_VER == 2 # define ACCESS_LATCH() # define ACCESS_PORT_IER() #else @@ -107,7 +113,16 @@ static inline void serial_do_portmux(void) return; } -#if defined(__ADSPBF51x__) +#if defined(__ADSPBF50x__) +# define DO_MUX(port, mux_tx, mux_rx, tx, rx) \ + bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~(PORT_x_MUX_##mux_tx##_MASK | PORT_x_MUX_##mux_rx##_MASK)) | PORT_x_MUX_##mux_tx##_FUNC_1 | PORT_x_MUX_##mux_rx##_FUNC_1); \ + bfin_write_PORT##port##_FER(bfin_read_PORT##port##_FER() | P##port##tx | P##port##rx); + switch (CONFIG_UART_CONSOLE) { + case 0: DO_MUX(G, 7, 7, 12, 13); break; /* Port G; mux 7; PG12 and PG13 */ + case 1: DO_MUX(F, 3, 3, 6, 7); break; /* Port F; mux 3; PF6 and PF7 */ + } + SSYNC(); +#elif defined(__ADSPBF51x__) # define DO_MUX(port, mux_tx, mux_rx, tx, rx) \ bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~(PORT_x_MUX_##mux_tx##_MASK | PORT_x_MUX_##mux_rx##_MASK)) | PORT_x_MUX_##mux_tx##_FUNC_2 | PORT_x_MUX_##mux_rx##_FUNC_2); \ bfin_write_PORT##port##_FER(bfin_read_PORT##port##_FER() | P##port##tx | P##port##rx); |