diff options
| author | Yuanquan Chen <B41889@freescale.com> | 2012-11-26 23:49:45 (GMT) |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2012-11-28 00:28:07 (GMT) |
| commit | c0a4e6b889a702cc2c8375619ce7b093f6b3b1de (patch) | |
| tree | c707baafbb5971ca6d826e4056fc5969e1f00169 /arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | |
| parent | 9760b274df8fdc5a6d124f3192535ebe281a78a6 (diff) | |
| download | u-boot-c0a4e6b889a702cc2c8375619ce7b093f6b3b1de.tar.xz | |
powerpc/p4080ds: fix PCI-e x8 link training down failure
Due to SerDes configuration error, if we set the PCI-e controller link width
as x8 in RCW and add a narrower width(such as x4, x2 or x1) PCI-e device to
PCI-e slot, it fails to train down to the PCI-e device's link width. According
to p4080ds errata PCIe-A003, we reset the PCI-e controller link width to x4 in
u-boot. Then it can train down to x2 or x1 width to make the PCI-e link between
RC and EP.
Signed-off-by: Yuanquan Chen <B41889@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c')
0 files changed, 0 insertions, 0 deletions