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| author | Wolfgang Denk <wd@denx.de> | 2012-07-08 17:16:14 (GMT) |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2012-07-08 17:16:14 (GMT) |
| commit | 8246ff864de38935ff34108856a37a2caf6cbefc (patch) | |
| tree | fb33f056c2ff6acd4619b7b0098d470c99bd1754 /arch/powerpc/cpu/mpc85xx/release.S | |
| parent | c8a90646adb1c7ca82e856c603ec964b32759d98 (diff) | |
| parent | feae34243f63fc319b40db7b92070a0718dc31a6 (diff) | |
| download | u-boot-8246ff864de38935ff34108856a37a2caf6cbefc.tar.xz | |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
* 'master' of git://git.denx.de/u-boot-mpc85xx:
powerpc/mpc85xx: Fix Handling the lack of L2 cache on P2040/P2040E
powerpc/mpc85xx: Workaround for erratum CPU_A011
powerpc/mpc85xx: Ignore E bit for SVR_SOC_VER()
powerpc/P4080: Check SVR for CPU22 workaround
lib/powerpc: addrmap_phys_to_virt() should return a pointer
powerpc/85xx: clean up P1022DS board configuration header file
powerpc/85xx: fdt_set_phy_handle() should return an error code
powerpc/85xx: minor clean-ups to the P2020DS board header file
powerpc/p1010rdb: add readme document for p1010rdb
powerpc/mpc85xx:NAND_SPL:Avoid IFC/eLBC Base address setting
powerpc/mpc85xx:Add debugger support for e500v2 SoC
powerpc/85xx:Fix NAND code base to support debugger
powerpc/85xx:Make debug exception vector accessible
powerpc/85xx:Fix MSR[DE] bit in MSR to support debugger
PATCH 1/4][v4] doc:Add documentation for e500 external debugger support
powerpc/p1010rdb: update mux config of p1010rdb board
powerpc/mpc85xx:Add BSC9131 RDB Support
powerpc/mpc85xx:Add BSC9131/BSC9130/BSC9231 Processor Support
powerpc/85xx: Add USB device-tree fixup for various platforms
Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/release.S')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/release.S | 39 |
1 files changed, 28 insertions, 11 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index c81e19c..1860684 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -143,23 +143,40 @@ __secondary_start_page: mtspr L1CSR2,r8 #endif -#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) - mfspr r8,L1CSR2 - oris r8,r8,(L1CSR2_DCWS)@h - mtspr L1CSR2,r8 +#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ + defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) + /* + * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0 + * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 + * also appleis to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1 + */ + mfspr r3,SPRN_SVR + rlwinm r6,r3,24,~0x800 /* clear E bit */ + + lis r5,SVR_P4080@h + ori r5,r5,SVR_P4080@l + cmpw r6,r5 + bne 1f + + rlwinm r3,r3,0,0xf0 + li r5,0x30 + cmpw r3,r5 + bge 2f +1: + mfspr r3,L1CSR2 + oris r3,r3,(L1CSR2_DCWS)@h + mtspr L1CSR2,r3 +2: #endif #ifdef CONFIG_BACKSIDE_L2_CACHE /* skip L2 setup on P2040/P2040E as they have no L2 */ - mfspr r2,SPRN_SVR + mfspr r3,SPRN_SVR + rlwinm r6,r3,24,~0x800 /* clear E bit of SVR */ + lis r3,SVR_P2040@h ori r3,r3,SVR_P2040@l - cmpw r2,r3 - beq 3f - - lis r3,SVR_P2040_E@h - ori r3,r3,SVR_P2040_E@l - cmpw r2,r3 + cmpw r6,r3 beq 3f /* Enable/invalidate the L2 cache */ |