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| author | Tom Rini <trini@ti.com> | 2013-08-13 13:14:02 (GMT) |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-08-13 13:14:02 (GMT) |
| commit | b98d934128bcd98106e764d2f492ac79c38ae53d (patch) | |
| tree | 5e078614fccb51f34fa8f7aa8d92c4f5f518b686 /arch/powerpc/cpu/mpc85xx/release.S | |
| parent | 67cafc0861477bf19a587508ed13f4538c7a281e (diff) | |
| parent | 3aab0cd852d7c9565c2559a7983cbb73852bac28 (diff) | |
| download | u-boot-b98d934128bcd98106e764d2f492ac79c38ae53d.tar.xz | |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/release.S')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/release.S | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index 15bbbc1..c15e83b 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -226,6 +226,21 @@ __secondary_start_page: 2: #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A005812 + /* + * A-005812 workaround sets bit 32 of SPR 976 for SoCs running in + * write shadow mode. This code should run after other code setting + * DCWS. + */ + mfspr r3,L1CSR2 + andis. r3,r3,(L1CSR2_DCWS)@h + beq 1f + mfspr r3, SPRN_HDBCR0 + oris r3, r3, 0x8000 + mtspr SPRN_HDBCR0, r3 +1: +#endif + #ifdef CONFIG_BACKSIDE_L2_CACHE /* skip L2 setup on P2040/P2040E as they have no L2 */ mfspr r3,SPRN_SVR |