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author | Prabhakar Kushwaha <prabhakar@freescale.com> | 2013-08-29 07:40:38 (GMT) |
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committer | York Sun <yorksun@freescale.com> | 2013-10-16 23:13:11 (GMT) |
commit | e982746844605e5155fbd2e0ce13c3ecf7fafe48 (patch) | |
tree | 2889b68a69a0976bca54441caa9fe6839451ac56 /arch/powerpc/cpu/mpc85xx/speed.c | |
parent | 0e61077b215aff9228a4d6ca746761b49380713c (diff) | |
download | u-boot-e982746844605e5155fbd2e0ce13c3ecf7fafe48.tar.xz |
powerpc/mpc85xx:Make L2 cache type independent of CHASSIS2
CHASSIS2 architecture never defines type of L2 cache present in SoC.
it is dependent upon the core present in the SoC.
for example,
- e6500 core has L2 cluster (Kibo)
- e5500 core has Backside L2 Cache
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/speed.c')
0 files changed, 0 insertions, 0 deletions