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| author | Tom Rini <trini@konsulko.com> | 2015-05-05 18:57:23 (GMT) |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2015-05-05 18:57:23 (GMT) |
| commit | d81572c272d4b0980fb9b8a02e1357090b002398 (patch) | |
| tree | 4b2f774d628ab51944f0ba1ff83c15ef6b082a0f /arch/powerpc/cpu/mpc85xx/start.S | |
| parent | 1131d4e22cf8f13d0dabaad7f1b84d9baffdfbd6 (diff) | |
| parent | 8b0044ff5942943eaa49935f49d5006b346a60f8 (diff) | |
| download | u-boot-d81572c272d4b0980fb9b8a02e1357090b002398.tar.xz | |
Merge git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/start.S')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/start.S | 35 |
1 files changed, 20 insertions, 15 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 28f04ee..e61d8e0 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -1664,41 +1664,46 @@ clear_bss: */ .globl trap_init trap_init: + mflr r11 + bl _GLOBAL_OFFSET_TABLE_-4 + mflr r12 + /* Update IVORs as per relocation */ mtspr IVPR,r3 - li r4,CriticalInput@l + lwz r4,CriticalInput@got(r12) mtspr IVOR0,r4 /* 0: Critical input */ - li r4,MachineCheck@l + lwz r4,MachineCheck@got(r12) mtspr IVOR1,r4 /* 1: Machine check */ - li r4,DataStorage@l + lwz r4,DataStorage@got(r12) mtspr IVOR2,r4 /* 2: Data storage */ - li r4,InstStorage@l + lwz r4,InstStorage@got(r12) mtspr IVOR3,r4 /* 3: Instruction storage */ - li r4,ExtInterrupt@l + lwz r4,ExtInterrupt@got(r12) mtspr IVOR4,r4 /* 4: External interrupt */ - li r4,Alignment@l + lwz r4,Alignment@got(r12) mtspr IVOR5,r4 /* 5: Alignment */ - li r4,ProgramCheck@l + lwz r4,ProgramCheck@got(r12) mtspr IVOR6,r4 /* 6: Program check */ - li r4,FPUnavailable@l + lwz r4,FPUnavailable@got(r12) mtspr IVOR7,r4 /* 7: floating point unavailable */ - li r4,SystemCall@l + lwz r4,SystemCall@got(r12) mtspr IVOR8,r4 /* 8: System call */ /* 9: Auxiliary processor unavailable(unsupported) */ - li r4,Decrementer@l + lwz r4,Decrementer@got(r12) mtspr IVOR10,r4 /* 10: Decrementer */ - li r4,IntervalTimer@l + lwz r4,IntervalTimer@got(r12) mtspr IVOR11,r4 /* 11: Interval timer */ - li r4,WatchdogTimer@l + lwz r4,WatchdogTimer@got(r12) mtspr IVOR12,r4 /* 12: Watchdog timer */ - li r4,DataTLBError@l + lwz r4,DataTLBError@got(r12) mtspr IVOR13,r4 /* 13: Data TLB error */ - li r4,InstructionTLBError@l + lwz r4,InstructionTLBError@got(r12) mtspr IVOR14,r4 /* 14: Instruction TLB error */ - li r4,DebugBreakpoint@l + lwz r4,DebugBreakpoint@got(r12) mtspr IVOR15,r4 /* 15: Debug */ + mtlr r11 blr .globl unlock_ram_in_cache |