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| author | York Sun <yorksun@freescale.com> | 2012-10-08 07:44:23 (GMT) |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2012-10-22 19:31:26 (GMT) |
| commit | 123922b1e583dc6bd6b8909af2d788f6e40a33a9 (patch) | |
| tree | ed286734f765f1b12624b4ea9b878b6e94173569 /arch/powerpc/cpu/mpc8xxx/ddr/options.c | |
| parent | 57495e4e5e70d6a4e9b8f053bdf099f9cdb363d2 (diff) | |
| download | u-boot-123922b1e583dc6bd6b8909af2d788f6e40a33a9.tar.xz | |
powerpc/mpc8xxx: Fix DDR driver handling quad-rank DIMMs and address calculation
Fix handling quad-rank DIMMs in a system with two DIMM slots and first
slot supports both dual-rank DIMM and quad-rank DIMM.
For systems with quad-rank DIMM and double dual-rank DIMMs, cs_config
registers need to be enabled to maintain proper ODT operation. The
inactive CS should have bnds registers cleared.
Fix the turnaround timing for systems with all chip-selects enabled. This
wasn't an issue before because DDR was running lower than 1600MT/s with
this interleaving mode.
Fix DDR address calculation. It wasn't an issue until we have multiple
controllers with each more than 4GB and interleaving is disabled.
It also fixes the message of DDR: 2 GiB (DDR3, 64-bit, CL=0.5, ECC off)
when debugging DDR and first DDR controller is disabled. With the fix,
the first enabled controller information will be displayed.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc8xxx/ddr/options.c')
| -rw-r--r-- | arch/powerpc/cpu/mpc8xxx/ddr/options.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/arch/powerpc/cpu/mpc8xxx/ddr/options.c index 13e4825..1188df9 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/options.c @@ -510,6 +510,14 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, } } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) { switch (pdimm[0].n_ranks) { +#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE + case 4: + pdodt = single_Q; + if (pdimm[1].n_ranks) + printf("Error: Quad- and Dual-rank DIMMs " + "cannot be used together\n"); + break; +#endif case 2: switch (pdimm[1].n_ranks) { case 2: @@ -912,6 +920,10 @@ done: "interleaving disabled!\n", ctrl_num); } #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2) +#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE + if (pdimm[0].n_ranks == 4) + break; +#endif if ((pdimm[0].n_ranks < 2) && (pdimm[1].n_ranks < 2)) { popts->ba_intlv_ctl = 0; printf("Not enough bank(chip-select) for " |