diff options
| author | york <yorksun@freescale.com> | 2010-07-02 22:25:53 (GMT) |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2010-07-26 18:16:09 (GMT) |
| commit | 5800e7ab32c200836e81ab2384817d93105561c5 (patch) | |
| tree | a8022cbb490f4abbe4aba4480928abde59c70404 /arch/powerpc/cpu/mpc8xxx/ddr/options.c | |
| parent | 076bff8f4746baf7c83b96049d97e9dd4454dace (diff) | |
| download | u-boot-5800e7ab32c200836e81ab2384817d93105561c5.tar.xz | |
powerpc/8xxx: Enable quad-rank DIMMs.
Previous code presumes each DIMM has up to two rank (chip select). Newer
DDR controller supports up to four chip select on one DIMM.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc8xxx/ddr/options.c')
| -rw-r--r-- | arch/powerpc/cpu/mpc8xxx/ddr/options.c | 17 |
1 files changed, 10 insertions, 7 deletions
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/arch/powerpc/cpu/mpc8xxx/ddr/options.c index ebbdb69..1d5f3e2 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/options.c @@ -274,14 +274,14 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { case FSL_DDR_CS0_CS1_CS2_CS3: #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) - if (pdimm[0].n_ranks != 4) { + if (pdimm[0].n_ranks < 4) { popts->ba_intlv_ctl = 0; printf("Not enough bank(chip-select) for " "CS0+CS1+CS2+CS3 on controller %d, " "force non-interleaving!\n", ctrl_num); } #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2) - if ((pdimm[0].n_ranks != 2) && (pdimm[1].n_ranks != 2)) { + if ((pdimm[0].n_ranks < 2) && (pdimm[1].n_ranks < 2)) { popts->ba_intlv_ctl = 0; printf("Not enough bank(chip-select) for " "CS0+CS1+CS2+CS3 on controller %d, " @@ -296,7 +296,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, #endif break; case FSL_DDR_CS0_CS1: - if (pdimm[0].n_ranks != 2) { + if (pdimm[0].n_ranks < 2) { popts->ba_intlv_ctl = 0; printf("Not enough bank(chip-select) for " "CS0+CS1 on controller %d, " @@ -305,13 +305,13 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, break; case FSL_DDR_CS2_CS3: #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) - if (pdimm[0].n_ranks != 4) { + if (pdimm[0].n_ranks < 4) { popts->ba_intlv_ctl = 0; printf("Not enough bank(chip-select) for CS2+CS3 " "on controller %d, force non-interleaving!\n", ctrl_num); } #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2) - if (pdimm[1].n_ranks != 2) { + if (pdimm[1].n_ranks < 2) { popts->ba_intlv_ctl = 0; printf("Not enough bank(chip-select) for CS2+CS3 " "on controller %d, force non-interleaving!\n", ctrl_num); @@ -320,14 +320,14 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, break; case FSL_DDR_CS0_CS1_AND_CS2_CS3: #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) - if (pdimm[0].n_ranks != 4) { + if (pdimm[0].n_ranks < 4) { popts->ba_intlv_ctl = 0; printf("Not enough bank(CS) for CS0+CS1 and " "CS2+CS3 on controller %d, " "force non-interleaving!\n", ctrl_num); } #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2) - if ((pdimm[0].n_ranks != 2)||(pdimm[1].n_ranks != 2)) { + if ((pdimm[0].n_ranks < 2) || (pdimm[1].n_ranks < 2)) { popts->ba_intlv_ctl = 0; printf("Not enough bank(CS) for CS0+CS1 and " "CS2+CS3 on controller %d, " @@ -341,6 +341,9 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, } } + if (pdimm[0].n_ranks == 4) + popts->quad_rank_present = 1; + fsl_ddr_board_options(popts, pdimm, ctrl_num); return 0; |