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authorTom Rini <trini@konsulko.com>2015-05-05 18:57:23 (GMT)
committerTom Rini <trini@konsulko.com>2015-05-05 18:57:23 (GMT)
commitd81572c272d4b0980fb9b8a02e1357090b002398 (patch)
tree4b2f774d628ab51944f0ba1ff83c15ef6b082a0f /arch/powerpc/cpu/ppc4xx/cache.S
parent1131d4e22cf8f13d0dabaad7f1b84d9baffdfbd6 (diff)
parent8b0044ff5942943eaa49935f49d5006b346a60f8 (diff)
downloadu-boot-d81572c272d4b0980fb9b8a02e1357090b002398.tar.xz
Merge git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'arch/powerpc/cpu/ppc4xx/cache.S')
-rw-r--r--arch/powerpc/cpu/ppc4xx/cache.S43
1 files changed, 0 insertions, 43 deletions
diff --git a/arch/powerpc/cpu/ppc4xx/cache.S b/arch/powerpc/cpu/ppc4xx/cache.S
index 2714c2f..93e8366 100644
--- a/arch/powerpc/cpu/ppc4xx/cache.S
+++ b/arch/powerpc/cpu/ppc4xx/cache.S
@@ -74,49 +74,6 @@ _GLOBAL(clean_dcache_range)
blr
/*
- * Write any modified data cache blocks out to memory and invalidate them.
- * Does not invalidate the corresponding instruction cache blocks.
- *
- * flush_dcache_range(unsigned long start, unsigned long stop)
- */
-_GLOBAL(flush_dcache_range)
- li r5,L1_CACHE_BYTES-1
- andc r3,r3,r5
- subf r4,r3,r4
- add r4,r4,r5
- srwi. r4,r4,L1_CACHE_SHIFT
- beqlr
- mtctr r4
-
-1: dcbf 0,r3
- addi r3,r3,L1_CACHE_BYTES
- bdnz 1b
- sync /* wait for dcbst's to get to ram */
- blr
-
-/*
- * Like above, but invalidate the D-cache. This is used by the 8xx
- * to invalidate the cache so the PPC core doesn't get stale data
- * from the CPM (no cache snooping here :-).
- *
- * invalidate_dcache_range(unsigned long start, unsigned long stop)
- */
-_GLOBAL(invalidate_dcache_range)
- li r5,L1_CACHE_BYTES-1
- andc r3,r3,r5
- subf r4,r3,r4
- add r4,r4,r5
- srwi. r4,r4,L1_CACHE_SHIFT
- beqlr
- mtctr r4
-
-1: dcbi 0,r3
- addi r3,r3,L1_CACHE_BYTES
- bdnz 1b
- sync /* wait for dcbi's to get to ram */
- blr
-
-/*
* 40x cores have 8K or 16K dcache and 32 byte line size.
* 44x has a 32K dcache and 32 byte line size.
* 8xx has 1, 2, 4, 8K variants.