diff options
author | Simon Glass <sjg@chromium.org> | 2012-12-13 20:48:50 (GMT) |
---|---|---|
committer | Tom Rini <trini@ti.com> | 2013-02-04 14:05:42 (GMT) |
commit | 45bae2e3cf6b0653a0c68526be51457f50750dd5 (patch) | |
tree | 0fd3a32072369e0a1490737087f27d626c3b6018 /arch/powerpc/cpu | |
parent | 609e6ec3f623f3c3aa2a056654fbc5886e092897 (diff) | |
download | u-boot-45bae2e3cf6b0653a0c68526be51457f50750dd5.tar.xz |
ppc: Move CONFIG_QE to arch_global_data
Move the quantative easing fields into arch_global_data and tidy up.
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/powerpc/cpu')
-rw-r--r-- | arch/powerpc/cpu/mpc83xx/speed.c | 5 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/speed.c | 4 |
2 files changed, 5 insertions, 4 deletions
diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index a40a055..ba8b285 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -495,7 +495,7 @@ int get_clocks(void) gd->arch.mem_sec_clk = mem_sec_clk; #endif #if defined(CONFIG_QE) - gd->qe_clk = qe_clk; + gd->arch.qe_clk = qe_clk; gd->arch.brg_clk = brg_clk; #endif #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ @@ -541,7 +541,8 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf(" Coherent System Bus: %-4s MHz\n", strmhz(buf, gd->arch.csb_clk)); #if defined(CONFIG_QE) - printf(" QE: %-4s MHz\n", strmhz(buf, gd->qe_clk)); + printf(" QE: %-4s MHz\n", + strmhz(buf, gd->arch.qe_clk)); printf(" BRG: %-4s MHz\n", strmhz(buf, gd->arch.brg_clk)); #endif diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 81c80e7..7173c07 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -394,8 +394,8 @@ int get_clocks (void) gd->arch.lbc_clk = sys_info.freqLocalBus; #ifdef CONFIG_QE - gd->qe_clk = sys_info.freqQE; - gd->arch.brg_clk = gd->qe_clk / 2; + gd->arch.qe_clk = sys_info.freqQE; + gd->arch.brg_clk = gd->arch.qe_clk / 2; #endif /* * The base clock for I2C depends on the actual SOC. Unfortunately, |