diff options
| author | York Sun <york.sun@nxp.com> | 2016-11-18 21:36:39 (GMT) |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-11-24 07:42:13 (GMT) |
| commit | 5449c98a2d64de50d16f53401445a4f96356adea (patch) | |
| tree | 45b599a66e4dffafd6b950420ed5b887d2ea172f /arch/powerpc/include | |
| parent | 6fcddd098543f9cc1c4750fbf957141bbd1abfbe (diff) | |
| download | u-boot-5449c98a2d64de50d16f53401445a4f96356adea.tar.xz | |
powerpc: T1042: Remove macro CONFIG_PPC_T1042
Replace CONFIG_PPC_T1042 with ARCH_T1024 in Kconfig and clean up
existing macros.
Signed-off-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/powerpc/include')
| -rw-r--r-- | arch/powerpc/include/asm/config_mpc85xx.h | 4 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/immap_85xx.h | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 7a65caa..8efc805 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -679,7 +679,7 @@ #define CONFIG_NUM_DDR_CONTROLLERS 1 #endif -#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_PPC_T1042) ||\ +#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) ||\ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_E5500 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ @@ -689,7 +689,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #ifdef CONFIG_SYS_FSL_DDR4 #define CONFIG_SYS_FSL_DDRC_GEN4 #endif -#if defined(CONFIG_ARCH_T1040) || defined(CONFIG_PPC_T1042) +#if defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) #define CONFIG_MAX_CPUS 4 #elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_MAX_CPUS 2 diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 4de9fd3..5d63228 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1776,7 +1776,7 @@ typedef struct ccsr_gur { #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000 -#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_PPC_T1042) ||\ +#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) ||\ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24 |