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| author | Tom Rini <trini@konsulko.com> | 2017-01-25 22:09:01 (GMT) |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-01-25 22:38:45 (GMT) |
| commit | 79a34b71c943a80af5c6d9a2af736fbb37dcc14c (patch) | |
| tree | c903d3136106e2a566c33eb1366f110220f4c366 /arch/powerpc/include | |
| parent | a8523a808fd05e4b1c1df63bc40744dd3fd318f4 (diff) | |
| parent | 76866600f544f00928ee9b5b2799a091ea9b80a7 (diff) | |
| download | u-boot-79a34b71c943a80af5c6d9a2af736fbb37dcc14c.tar.xz | |
Merge git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'arch/powerpc/include')
| -rw-r--r-- | arch/powerpc/include/asm/fsl_pci.h | 4 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/processor.h | 1 |
2 files changed, 4 insertions, 1 deletions
diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h index 8bee8ca..cad341e 100644 --- a/arch/powerpc/include/asm/fsl_pci.h +++ b/arch/powerpc/include/asm/fsl_pci.h @@ -79,7 +79,9 @@ typedef struct ccsr_pci { u32 pme_msg_dis; /* 0x024 - PCIE PME & message disable register */ u32 pme_msg_int_en; /* 0x028 - PCIE PME & message interrupt enable register */ u32 pm_command; /* 0x02c - PCIE PM Command register */ - char res4[3016]; /* (- #xbf8 #x30)3016 */ + char res3[2188]; /* (0x8bc - 0x30 = 2188) */ + u32 dbi_ro_wr_en; /* 0x8bc - DBI read only write enable reg */ + char res4[824]; /* (0xbf8 - 0x8c0 = 824) */ u32 block_rev1; /* 0xbf8 - PCIE Block Revision register 1 */ u32 block_rev2; /* 0xbfc - PCIE Block Revision register 2 */ diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index fbf72bb..81bae6f 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -501,6 +501,7 @@ #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ #define SPRN_L1CSR2 0x25e /* L1 Data Cache Control and Status Register 2 */ #define L1CSR2_DCWS 0x40000000 /* Data Cache Write Shadow */ +#define L1CSR2_DCSTASHID 0x000003ff /* Data Cache Stash ID */ #define SPRN_L2CSR0 0x3f9 /* L2 Data Cache Control and Status Register 0 */ #define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */ #define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */ |