diff options
| author | York Sun <york.sun@nxp.com> | 2016-11-21 21:41:30 (GMT) |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-11-24 07:42:16 (GMT) |
| commit | cdb72c5212c54dba2275c132b14e0df77d2040a9 (patch) | |
| tree | 6907515592bab590476a82ff2abfb40c0c249594 /arch/powerpc/include | |
| parent | 26bc57da0ac1ed5769e53b0ef561fd4f08c020c7 (diff) | |
| download | u-boot-cdb72c5212c54dba2275c132b14e0df77d2040a9.tar.xz | |
powerpc: T4080: Drop configuration for T4080
There is no T4080 target. Drop related macros.
Signed-off-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/powerpc/include')
| -rw-r--r-- | arch/powerpc/include/asm/config_mpc85xx.h | 6 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/immap_85xx.h | 6 |
2 files changed, 3 insertions, 9 deletions
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 0d8eb46..2619562 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -545,8 +545,7 @@ #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 #define CONFIG_ESDHC_HC_BLK_ADDR -#elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) || \ - defined(CONFIG_PPC_T4080) +#elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) #define CONFIG_E6500 #define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ @@ -571,9 +570,6 @@ #if defined(CONFIG_ARCH_T4160) #define CONFIG_MAX_CPUS 8 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } -#elif defined(CONFIG_PPC_T4080) -#define CONFIG_MAX_CPUS 4 -#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1 } #endif #endif #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 75868fa..786e4f6 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1759,8 +1759,7 @@ typedef struct ccsr_gur { /* use reserved bits 18~23 as scratch space to host DDR PLL ratio */ #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT 8 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f -#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) || \ - defined(CONFIG_PPC_T4080) +#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000 @@ -1875,8 +1874,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000 #endif -#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) || \ - defined(CONFIG_PPC_T4080) +#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) #define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */ #define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000 #define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000 |