diff options
| author | Christophe Leroy <christophe.leroy@c-s.fr> | 2017-07-06 14:49:56 (GMT) |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-07-08 19:55:33 (GMT) |
| commit | 73bc94c6b7f73c2d22f43daaebfe5ddcb0948ee7 (patch) | |
| tree | 8af57e04d5702dd18b6a34ddb468205b201228bf /arch/powerpc | |
| parent | ba3da7348ac9aaa1cc0a9ccbc8b3c9367d87ca4b (diff) | |
| download | u-boot-73bc94c6b7f73c2d22f43daaebfe5ddcb0948ee7.tar.xz | |
powerpc, 8xx: Implement GLL2 ERRATA
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Acked-by: Wolfgang Denk <wd@denx.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
Diffstat (limited to 'arch/powerpc')
| -rw-r--r-- | arch/powerpc/cpu/mpc8xx/cpu_init.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c index cf12809..a51596a 100644 --- a/arch/powerpc/cpu/mpc8xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c @@ -51,6 +51,26 @@ void cpu_init_f(immap_t __iomem *immr) clrsetbits_be32(&immr->im_clkrst.car_sccr, ~SCCR_MASK, CONFIG_SYS_SCCR); + /* + * MPC866/885 ERRATA GLL2 + * Description: + * In 1:2:1 mode, when HRESET is detected at the positive edge of + * EXTCLK, then there will be a loss of phase between + * EXTCLK and CLKOUT. + * + * Workaround: + * Reprogram the SCCR: + * 1. Write 1'b00 to SCCR[EBDF]. + * 2. Write 1'b01 to SCCR[EBDF]. + * 3. Rewrite the desired value to the PLPRCR register. + */ + reg = in_be32(&immr->im_clkrst.car_sccr); + /* Are we in mode 1:2:1 ? */ + if ((reg & SCCR_EBDF11) == SCCR_EBDF01) { + clrbits_be32(&immr->im_clkrst.car_sccr, SCCR_EBDF11); + setbits_be32(&immr->im_clkrst.car_sccr, SCCR_EBDF01); + } + /* PLL (CPU clock) settings (15-30) */ out_be32(&immr->im_clkrstk.cark_plprcrk, KAPWR_KEY); |