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author | Bin Meng <bmeng.cn@gmail.com> | 2015-05-25 14:35:04 (GMT) |
---|---|---|
committer | Simon Glass <sjg@chromium.org> | 2015-06-04 08:39:39 (GMT) |
commit | 9c7dea602edd9027848d312e9b3b69f06c15f163 (patch) | |
tree | 4893732c170a3a889b819482f7003491ecbac11c /arch/x86/cpu/Makefile | |
parent | 2aa3a7fb1c24afd4c0e12360acccf3234d8fe019 (diff) | |
download | u-boot-9c7dea602edd9027848d312e9b3b69f06c15f163.tar.xz |
x86: Refactor PIRQ routing support
PIRQ routing is pretty much common in Intel chipset. It has several
PIRQ links (normally 8) and corresponding registers (either in PCI
configuration space or memory-mapped IBASE) to configure the legacy
8259 IRQ vector mapping. Refactor current Queensbay PIRQ routing
support using device tree and move it to a common place, so that we
can easily add PIRQ routing support on a new platform.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/cpu/Makefile')
-rw-r--r-- | arch/x86/cpu/Makefile | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index 307545a..7ff05e6 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -19,7 +19,7 @@ obj-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += ivybridge/ obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/ obj-$(CONFIG_INTEL_QUARK) += quark/ obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/ -obj-y += lapic.o +obj-y += irq.o lapic.o obj-$(CONFIG_SMP) += mp_init.o obj-y += mtrr.o obj-$(CONFIG_PCI) += pci.o |