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| author | Simon Glass <sjg@chromium.org> | 2016-03-12 05:06:53 (GMT) |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2016-03-17 02:27:24 (GMT) |
| commit | 1223d737a38dab7f05e7d62a3c931e28aa1e1495 (patch) | |
| tree | 060f7cdd1fdfd59d2de13c3154c23066be7a2704 /arch/x86/cpu/ivybridge/Makefile | |
| parent | 342727ace6fd3dd5c96bb9342eabe96614ed208a (diff) | |
| download | u-boot-1223d737a38dab7f05e7d62a3c931e28aa1e1495.tar.xz | |
x86: Move cache-as-RAM code into a common location
This cache-as-RAM (CAR) code is common to several Intel chips. Create a new
intel_common directory and move it in there.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86/cpu/ivybridge/Makefile')
| -rw-r--r-- | arch/x86/cpu/ivybridge/Makefile | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile index 9203219..b117f0d 100644 --- a/arch/x86/cpu/ivybridge/Makefile +++ b/arch/x86/cpu/ivybridge/Makefile @@ -7,7 +7,6 @@ ifdef CONFIG_HAVE_FSP obj-y += fsp_configs.o ivybridge.o else -obj-y += car.o obj-y += cpu.o obj-y += early_me.o obj-y += gma.o |