x86: ivybridge: Add support for BD82x6x PCH

Add basic setup for the PCH.

Signed-off-by: Simon Glass <sjg@chromium.org>

1 files changed, 40 insertions, 0 deletions

diff --git a/arch/x86/cpu/ivybridge/pci.c b/arch/x86/cpu/ivybridge/pci.c
index c1ae658..452d1c3 100644
--- a/arch/x86/cpu/ivybridge/pci.c
+++ b/arch/x86/cpu/ivybridge/pci.c
@@ -12,6 +12,8 @@
 #include <common.h>
 #include <pci.h>
 #include <asm/pci.h>
+#include <asm/arch/bd82x6x.h>
+#include <asm/arch/pch.h>
 
 static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev,
 			      struct pci_config_table *table)
@@ -58,3 +60,41 @@ void board_pci_setup_hose(struct pci_controller *hose)
 
 	hose->region_count = 3;
 }
+
+int board_pci_pre_scan(struct pci_controller *hose)
+{
+	pci_dev_t dev;
+	u16 reg16;
+
+	bd82x6x_init();
+
+	reg16 = 0xff;
+	dev = PCH_DEV;
+	reg16 = pci_read_config16(dev, PCI_COMMAND);
+	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+	pci_write_config16(dev, PCI_COMMAND, reg16);
+
+	/*
+	* Clear non-reserved bits in status register.
+	*/
+	pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
+	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
+	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
+
+	pci_write_bar32(hose, dev, 0, 0xf0000000);
+
+	return 0;
+}
+
+int board_pci_post_scan(struct pci_controller *hose)
+{
+	int ret;
+
+	ret = bd82x6x_init_pci_devices();
+	if (ret) {
+		printf("bd82x6x_init_pci_devices() failed: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}