diff options
| author | Simon Glass <sjg@chromium.org> | 2016-01-19 03:19:21 (GMT) |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2016-01-24 04:07:17 (GMT) |
| commit | f2b85ab5e6a91e29c1d64304be371753d75ed172 (patch) | |
| tree | c7e65743fd66f6a06f425bd8bf7bc643f807eefe /arch/x86/cpu/ivybridge | |
| parent | fffe25db04b428f34b72264ff50c40f395fcd936 (diff) | |
| download | u-boot-f2b85ab5e6a91e29c1d64304be371753d75ed172.tar.xz | |
dm: x86: spi: Convert ICH SPI driver to driver model PCI API
At present this SPI driver works by searching the PCI buses for its
peripheral. It also uses the legacy PCI API.
In addition the driver has code to determine the type of Intel PCH that is
used (version 7 or version 9). Now that we have proper PCH drivers we can
use those to obtain the information we need.
While the device tree has a node for the SPI peripheral it is not in the
right place. It should be on the PCI bus as a sub-peripheral of the LPC
device.
Update the device tree files to show the SPI controller within the PCH, so
that PCI access works as expected.
This patch includes Bin's fix-up patch from here:
https://patchwork.ozlabs.org/patch/569478/
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86/cpu/ivybridge')
| -rw-r--r-- | arch/x86/cpu/ivybridge/bd82x6x.c | 47 |
1 files changed, 46 insertions, 1 deletions
diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index 434dfd6..c000aca 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -3,12 +3,12 @@ * * SPDX-License-Identifier: GPL-2.0+ */ - #include <common.h> #include <dm.h> #include <errno.h> #include <fdtdec.h> #include <malloc.h> +#include <pch.h> #include <asm/lapic.h> #include <asm/pci.h> #include <asm/arch/bd82x6x.h> @@ -16,6 +16,8 @@ #include <asm/arch/pch.h> #include <asm/arch/sandybridge.h> +#define BIOS_CTRL 0xdc + void bd82x6x_pci_init(pci_dev_t dev) { u16 reg16; @@ -96,6 +98,7 @@ static int bd82x6x_probe(struct udevice *dev) return 0; } +/* TODO(sjg@chromium.org): Move this to the PCH init() method */ int bd82x6x_init(void) { const void *blob = gd->fdt_blob; @@ -116,6 +119,47 @@ int bd82x6x_init(void) return 0; } +static int bd82x6x_pch_get_sbase(struct udevice *dev, ulong *sbasep) +{ + u32 rcba; + + dm_pci_read_config32(dev, PCH_RCBA, &rcba); + /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */ + rcba = rcba & 0xffffc000; + *sbasep = rcba + 0x3800; + + return 0; +} + +static enum pch_version bd82x6x_pch_get_version(struct udevice *dev) +{ + return PCHV_9; +} + +static int bd82x6x_set_spi_protect(struct udevice *dev, bool protect) +{ + uint8_t bios_cntl; + + /* Adjust the BIOS write protect and SMM BIOS Write Protect Disable */ + dm_pci_read_config8(dev, BIOS_CTRL, &bios_cntl); + if (protect) { + bios_cntl &= ~BIOS_CTRL_BIOSWE; + bios_cntl |= BIT(5); + } else { + bios_cntl |= BIOS_CTRL_BIOSWE; + bios_cntl &= ~BIT(5); + } + dm_pci_write_config8(dev, BIOS_CTRL, bios_cntl); + + return 0; +} + +static const struct pch_ops bd82x6x_pch_ops = { + .get_sbase = bd82x6x_pch_get_sbase, + .get_version = bd82x6x_pch_get_version, + .set_spi_protect = bd82x6x_set_spi_protect, +}; + static const struct udevice_id bd82x6x_ids[] = { { .compatible = "intel,bd82x6x" }, { } @@ -126,4 +170,5 @@ U_BOOT_DRIVER(bd82x6x_drv) = { .id = UCLASS_PCH, .of_match = bd82x6x_ids, .probe = bd82x6x_probe, + .ops = &bd82x6x_pch_ops, }; |