diff options
| author | Simon Glass <sjg@chromium.org> | 2016-01-17 23:11:55 (GMT) |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2016-01-24 04:09:42 (GMT) |
| commit | 278d3a4444cd89214be7951d7493716990361b7b (patch) | |
| tree | 9cd5f02168c168107911badd5d801df59f186e9b /arch/x86/dts | |
| parent | 1605b10032eb073b6854fdeddbf455bf403eb6f1 (diff) | |
| download | u-boot-278d3a4444cd89214be7951d7493716990361b7b.tar.xz | |
x86: ivybridge: Drop special EHCI init
This is not needed. On reset wake-on-disconnect is already set. It may a
problem during a soft reset or resume, but for now it does not seem
important. Also drop the command register update since PCI auto-config
does it for us.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86/dts')
| -rw-r--r-- | arch/x86/dts/chromebook_link.dts | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index 329eae8..662e5d9 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -12,6 +12,8 @@ aliases { spi0 = "/pci/pch/spi"; + usb0 = &usb_0; + usb1 = &usb_1; }; config { @@ -226,6 +228,16 @@ u-boot,dm-pre-reloc; }; + usb_1: usb@1a,0 { + reg = <0x0000d000 0 0 0 0>; + compatible = "ehci-pci"; + }; + + usb_0: usb@1d,0 { + reg = <0x0000e800 0 0 0 0>; + compatible = "ehci-pci"; + }; + pch@1f,0 { reg = <0x0000f800 0 0 0 0>; compatible = "intel,bd82x6x", "intel,pch9"; |