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| author | Simon Glass <sjg@chromium.org> | 2016-11-26 03:16:02 (GMT) |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2016-12-19 19:09:55 (GMT) |
| commit | b215fbd868b4f0b55674f66a69c46edd5d9d9352 (patch) | |
| tree | 801fd5d870c4cf780e829b9b89c3d1de990ef3bb /arch/x86/dts | |
| parent | 61b994a386eb6f631dc1c2194d4cce9b1a43542c (diff) | |
| download | u-boot-b215fbd868b4f0b55674f66a69c46edd5d9d9352.tar.xz | |
x86: Use binman all x86 boards
Change x86 boards to use binman to produce the ROM. This involves adding the
image definition to the device tree and using it in the Makefile. The
existing ifdtool features are no-longer needed.
Note that the u-boot.dtsi file is common and is used for all x86 boards which
use microcode. A separate emulation-u-boot-dtsi is used for the others.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86/dts')
| -rw-r--r-- | arch/x86/dts/emulation-u-boot.dtsi | 18 | ||||
| -rw-r--r-- | arch/x86/dts/u-boot.dtsi | 62 |
2 files changed, 80 insertions, 0 deletions
diff --git a/arch/x86/dts/emulation-u-boot.dtsi b/arch/x86/dts/emulation-u-boot.dtsi new file mode 100644 index 0000000..56d34af --- /dev/null +++ b/arch/x86/dts/emulation-u-boot.dtsi @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2016 Google, Inc + * Written by Simon Glass <sjg@chromium.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <u-boot.dtsi> + +#ifdef CONFIG_ROM_SIZE +/ { + binman { + u-boot-with-ucode-ptr { + optional-ucode; + }; + }; +}; +#endif diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi new file mode 100644 index 0000000..724913f --- /dev/null +++ b/arch/x86/dts/u-boot.dtsi @@ -0,0 +1,62 @@ +/* + * Copyright (C) 2016 Google, Inc + * Written by Simon Glass <sjg@chromium.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> + +#ifdef CONFIG_ROM_SIZE +/ { + binman { + filename = "u-boot.rom"; + end-at-4gb; + sort-by-pos; + pad-byte = <0xff>; + size = <CONFIG_ROM_SIZE>; +#ifdef CONFIG_HAVE_INTEL_ME + intel-descriptor { + }; + intel-me { + }; +#endif + u-boot-with-ucode-ptr { + pos = <CONFIG_SYS_TEXT_BASE>; + }; + u-boot-dtb-with-ucode { + }; + u-boot-ucode { + align = <16>; + }; +#ifdef CONFIG_HAVE_MRC + intel-mrc { + pos = <CONFIG_X86_MRC_ADDR>; + }; +#endif +#ifdef CONFIG_HAVE_FSP + intel-fsp { + pos = <CONFIG_FSP_ADDR>; + }; +#endif +#ifdef CONFIG_HAVE_CMC + intel-cmc { + pos = <CONFIG_CMC_ADDR>; + }; +#endif +#ifdef CONFIG_HAVE_VGA_BIOS + intel-vga { + pos = <CONFIG_VGA_BIOS_ADDR>; + }; +#endif +#ifdef CONFIG_HAVE_REFCODE + intel-refcode { + pos = <CONFIG_X86_REFCODE_ADDR>; + }; +#endif + x86-start16 { + pos = <CONFIG_SYS_X86_START16>; + }; + }; +}; +#endif |