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authorBin Meng <bmeng.cn@gmail.com>2016-05-26 02:19:07 (GMT)
committerBin Meng <bmeng.cn@gmail.com>2016-05-30 02:21:12 (GMT)
commit3498cc9775e255875ae30ecfb4e29ea1220923a3 (patch)
treea2adeb4a11da16c0e937037777ac05ae122705de /arch/x86/include/asm/acpi
parent0d71511a2ae03aeb3794a0461bd8c14752438c7f (diff)
downloadu-boot-3498cc9775e255875ae30ecfb4e29ea1220923a3.tar.xz
x86: acpi: Make irqroute.asl common
The irqroute.asl file is already common enough to all x86 platforms. Platform ASL files need only provide a irqroute.h to describe how internal PCI devices and PCIe downstream port devices' INTx pins are routed to which PIRQ pin. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/include/asm/acpi')
-rw-r--r--arch/x86/include/asm/acpi/irq_helper.h111
-rw-r--r--arch/x86/include/asm/acpi/irqroute.asl48
2 files changed, 159 insertions, 0 deletions
diff --git a/arch/x86/include/asm/acpi/irq_helper.h b/arch/x86/include/asm/acpi/irq_helper.h
new file mode 100644
index 0000000..f0b3a6b
--- /dev/null
+++ b/arch/x86/include/asm/acpi/irq_helper.h
@@ -0,0 +1,111 @@
+/*
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2014 Sage Electronics Engineering, LLC.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/include/soc/irq_helper.h
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * This file intentionally gets included multiple times, to set pic and apic
+ * modes, so should not have guard statements added.
+ */
+
+/*
+ * This file will use irqroute.asl and irqroute.h to generate the ACPI IRQ
+ * routing for the platform being compiled.
+ *
+ * This method uses #defines in irqroute.h along with the macros contained
+ * in this file to generate an IRQ routing for each PCI device in the system.
+ */
+
+#undef PCI_DEV_PIRQ_ROUTES
+#undef PCI_DEV_PIRQ_ROUTE
+#undef ACPI_DEV_IRQ
+#undef PCIE_BRIDGE_DEV
+#undef RP_IRQ_ROUTES
+#undef ROOTPORT_METHODS
+#undef ROOTPORT_IRQ_ROUTES
+#undef RP_METHOD
+
+#if defined(PIC_MODE)
+
+#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \
+ Package() { ## dev_ ## ffff, pin_, \_SB.PCI0.LPCB.LNK ## pin_name_, 0 }
+
+#define RP_IRQ_ROUTES(prefix_, func_, a_, b_, c_, d_) \
+Name(prefix_ ## func_ ## P, Package() \
+{ \
+ ACPI_DEV_IRQ(0x0000, 0, a_), \
+ ACPI_DEV_IRQ(0x0000, 1, b_), \
+ ACPI_DEV_IRQ(0x0000, 2, c_), \
+ ACPI_DEV_IRQ(0x0000, 3, d_), \
+})
+
+/* define as blank so ROOTPORT_METHODS only gets inserted once */
+#define ROOTPORT_METHODS(prefix_, dev_)
+
+#else /* defined(PIC_MODE) */
+
+#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \
+ Package() { ## dev_ ## ffff, pin_, 0, PIRQ ## pin_name_ ## _APIC_IRQ }
+
+#define RP_IRQ_ROUTES(prefix_, func_, a_, b_, c_, d_) \
+Name(prefix_ ## func_ ## A, Package() \
+{ \
+ ACPI_DEV_IRQ(0x0000, 0, a_), \
+ ACPI_DEV_IRQ(0x0000, 1, b_), \
+ ACPI_DEV_IRQ(0x0000, 2, c_), \
+ ACPI_DEV_IRQ(0x0000, 3, d_), \
+})
+
+#define ROOTPORT_METHODS(prefix_, dev_) \
+ RP_METHOD(prefix_, dev_, 0) \
+ RP_METHOD(prefix_, dev_, 1) \
+ RP_METHOD(prefix_, dev_, 2) \
+ RP_METHOD(prefix_, dev_, 3) \
+ RP_METHOD(prefix_, dev_, 4) \
+ RP_METHOD(prefix_, dev_, 5) \
+ RP_METHOD(prefix_, dev_, 6) \
+ RP_METHOD(prefix_, dev_, 7)
+
+#endif /* defined(PIC_MODE) */
+
+#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \
+ ACPI_DEV_IRQ(dev_, 0, a_), \
+ ACPI_DEV_IRQ(dev_, 1, b_), \
+ ACPI_DEV_IRQ(dev_, 2, c_), \
+ ACPI_DEV_IRQ(dev_, 3, d_)
+
+#define PCIE_BRIDGE_DEV(prefix_, dev_, a_, b_, c_, d_) \
+ ROOTPORT_IRQ_ROUTES(prefix_, a_, b_, c_, d_) \
+ ROOTPORT_METHODS(prefix_, dev_)
+
+#define ROOTPORT_IRQ_ROUTES(prefix_, a_, b_, c_, d_) \
+ RP_IRQ_ROUTES(prefix_, 0, a_, b_, c_, d_) \
+ RP_IRQ_ROUTES(prefix_, 1, b_, c_, d_, a_) \
+ RP_IRQ_ROUTES(prefix_, 2, c_, d_, a_, b_) \
+ RP_IRQ_ROUTES(prefix_, 3, d_, a_, b_, c_) \
+ RP_IRQ_ROUTES(prefix_, 4, a_, b_, c_, d_) \
+ RP_IRQ_ROUTES(prefix_, 5, b_, c_, d_, a_) \
+ RP_IRQ_ROUTES(prefix_, 6, c_, d_, a_, b_) \
+ RP_IRQ_ROUTES(prefix_, 7, d_, a_, b_, c_)
+
+#define RP_METHOD(prefix_, dev_, func_)\
+Device (prefix_ ## 0 ## func_) \
+{ \
+ Name(_ADR, dev_ ## 000 ## func_) \
+ Name(_PRW, Package() { 0, 0 }) \
+ Method(_PRT) { \
+ If (PICM) { \
+ Return (prefix_ ## func_ ## A) \
+ } Else { \
+ Return (prefix_ ## func_ ## P) \
+ } \
+ } \
+}
+
+/* SoC specific PIRQ route configuration */
+#include <asm/arch/acpi/irqroute.h>
diff --git a/arch/x86/include/asm/acpi/irqroute.asl b/arch/x86/include/asm/acpi/irqroute.asl
new file mode 100644
index 0000000..64d3820
--- /dev/null
+++ b/arch/x86/include/asm/acpi/irqroute.asl
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/irqroute.asl
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+Name(\PICM, 0)
+
+/*
+ * The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local APIC/IOAPIC configuration.
+ */
+Method(\_PIC, 1)
+{
+ /* Remember the OS' IRQ routing choice */
+ Store(Arg0, PICM)
+}
+
+/* PCI interrupt routing */
+Method(_PRT) {
+ If (PICM) {
+ Return (Package() {
+ #undef PIC_MODE
+ #include "irq_helper.h"
+ PCI_DEV_PIRQ_ROUTES
+ })
+ } Else {
+ Return (Package() {
+ #define PIC_MODE
+ #include "irq_helper.h"
+ PCI_DEV_PIRQ_ROUTES
+ })
+ }
+
+}
+
+/* PCIe downstream ports interrupt routing */
+PCIE_BRIDGE_IRQ_ROUTES
+#undef PIC_MODE
+#include "irq_helper.h"
+PCIE_BRIDGE_IRQ_ROUTES