summaryrefslogtreecommitdiff
path: root/arch/x86/include/asm/arch-quark/iomap.h
diff options
context:
space:
mode:
authorBin Meng <bmeng.cn@gmail.com>2016-05-26 02:19:10 (GMT)
committerBin Meng <bmeng.cn@gmail.com>2016-05-30 02:21:12 (GMT)
commit48cf8b834603253440496a2356d192f8e4138d14 (patch)
tree9a32f5ea7b7c72e3ad9fb50a1f19f92b41c79bf5 /arch/x86/include/asm/arch-quark/iomap.h
parentec3791322159accacb06213a660a63b9ffb84f31 (diff)
downloadu-boot-48cf8b834603253440496a2356d192f8e4138d14.tar.xz
x86: quark: Add platform ASL files
This adds basic quark platform ASL files. They are intended to be included in dsdt.asl of any board that is based on this platform. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/include/asm/arch-quark/iomap.h')
-rw-r--r--arch/x86/include/asm/arch-quark/iomap.h47
1 files changed, 47 insertions, 0 deletions
diff --git a/arch/x86/include/asm/arch-quark/iomap.h b/arch/x86/include/asm/arch-quark/iomap.h
new file mode 100644
index 0000000..fd1ef98
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/iomap.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _QUARK_IOMAP_H_
+#define _QUARK_IOMAP_H_
+
+/* Memory Mapped IO bases */
+
+/* ESRAM */
+#define ESRAM_BASE_ADDRESS CONFIG_ESRAM_BASE
+#define ESRAM_BASE_SIZE ESRAM_SIZE
+
+/* PCI Configuration Space */
+#define MCFG_BASE_ADDRESS CONFIG_PCIE_ECAM_BASE
+#define MCFG_BASE_SIZE 0x10000000
+
+/* High Performance Event Timer */
+#define HPET_BASE_ADDRESS 0xfed00000
+#define HPET_BASE_SIZE 0x400
+
+/* Root Complex Base Address */
+#define RCBA_BASE_ADDRESS CONFIG_RCBA_BASE
+#define RCBA_BASE_SIZE 0x4000
+
+/* IO Port bases */
+#define ACPI_PM1_BASE_ADDRESS CONFIG_ACPI_PM1_BASE
+#define ACPI_PM1_BASE_SIZE 0x10
+
+#define ACPI_PBLK_BASE_ADDRESS CONFIG_ACPI_PBLK_BASE
+#define ACPI_PBLK_BASE_SIZE 0x10
+
+#define SPI_DMA_BASE_ADDRESS CONFIG_SPI_DMA_BASE
+#define SPI_DMA_BASE_SIZE 0x10
+
+#define GPIO_BASE_ADDRESS CONFIG_GPIO_BASE
+#define GPIO_BASE_SIZE 0x80
+
+#define ACPI_GPE0_BASE_ADDRESS CONFIG_ACPI_GPE0_BASE
+#define ACPI_GPE0_BASE_SIZE 0x40
+
+#define WDT_BASE_ADDRESS CONFIG_WDT_BASE
+#define WDT_BASE_SIZE 0x40
+
+#endif /* _QUARK_IOMAP_H_ */