diff options
| author | Andy Shevchenko <andriy.shevchenko@linux.intel.com> | 2017-02-17 13:49:00 (GMT) |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2017-02-21 07:10:56 (GMT) |
| commit | 308c75e08deac2933fbc63a1e9521343e710279c (patch) | |
| tree | 72c399b1ea5778d48335b809a396d03611cf2e22 /arch/x86 | |
| parent | 20bfac0599bd7eaad901287fe4a343f9fd6cf6ef (diff) | |
| download | u-boot-308c75e08deac2933fbc63a1e9521343e710279c.tar.xz | |
x86: Intel MID platforms has no microcode update
There is no microcode update available for SoCs used on Intel MID
platforms.
Use conditional to bypass it.
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Diffstat (limited to 'arch/x86')
| -rw-r--r-- | arch/x86/cpu/mp_init.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c index 988073c..cfd9bb4 100644 --- a/arch/x86/cpu/mp_init.c +++ b/arch/x86/cpu/mp_init.c @@ -248,7 +248,8 @@ static int load_sipi_vector(atomic_t **ap_countp, int num_cpus) if (!stack) return -ENOMEM; params->stack_top = (u32)(stack + size); -#if !defined(CONFIG_QEMU) && !defined(CONFIG_HAVE_FSP) +#if !defined(CONFIG_QEMU) && !defined(CONFIG_HAVE_FSP) && \ + !defined(CONFIG_INTEL_MID) params->microcode_ptr = ucode_base; debug("Microcode at %x\n", params->microcode_ptr); #endif |