diff options
author | Bin Meng <bmeng.cn@gmail.com> | 2015-10-12 04:37:38 (GMT) |
---|---|---|
committer | Simon Glass <sjg@chromium.org> | 2015-10-21 13:46:27 (GMT) |
commit | bfa95c538b8b7d9384141f3c88021aa9d941ba54 (patch) | |
tree | 9ac4093a1402f0523ff3e714d2bfa92805f7f324 /arch/x86 | |
parent | 2fe66dbcbc1793dc199d90c4d66acaad981f9820 (diff) | |
download | u-boot-bfa95c538b8b7d9384141f3c88021aa9d941ba54.tar.xz |
x86: Add various minor tidy-ups in mrccache codes
Fix some nits, improve some comments and reorder some codes
a little bit.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86')
-rw-r--r-- | arch/x86/include/asm/mrccache.h | 20 | ||||
-rw-r--r-- | arch/x86/lib/mrccache.c | 14 |
2 files changed, 16 insertions, 18 deletions
diff --git a/arch/x86/include/asm/mrccache.h b/arch/x86/include/asm/mrccache.h index ff41b8a..2fd9082 100644 --- a/arch/x86/include/asm/mrccache.h +++ b/arch/x86/include/asm/mrccache.h @@ -1,17 +1,17 @@ /* - * Copyright (c) 2014 Google, Inc + * Copyright (C) 2014 Google, Inc * * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef _ASM_ARCH_MRCCACHE_H -#define _ASM_ARCH_MRCCACHE_H +#ifndef _ASM_MRCCACHE_H +#define _ASM_MRCCACHE_H #define MRC_DATA_ALIGN 0x1000 -#define MRC_DATA_SIGNATURE (('M' << 0) | ('R' << 8) | ('C' << 16) | \ - ('D'<<24)) +#define MRC_DATA_SIGNATURE (('M' << 0) | ('R' << 8) | \ + ('C' << 16) | ('D'<<24)) -__packed struct mrc_data_container { +struct __packed mrc_data_container { u32 signature; /* "MRCD" */ u32 data_size; /* Size of the 'data' field */ u32 checksum; /* IP style checksum */ @@ -28,7 +28,7 @@ struct udevice; * This searches the MRC cache region looking for the latest record to use * for setting up SDRAM * - * @entry: Information about the position and size of the MRC cache + * @entry: Position and size of MRC cache in SPI flash * @return pointer to latest record, or NULL if none */ struct mrc_data_container *mrccache_find_current(struct fmap_entry *entry); @@ -36,8 +36,8 @@ struct mrc_data_container *mrccache_find_current(struct fmap_entry *entry); /** * mrccache_update() - update the MRC cache with a new record * - * This writes a new record to the end of the MRC cache. If the new record is - * the same as the latest record then the write is skipped + * This writes a new record to the end of the MRC cache region. If the new + * record is the same as the latest record then the write is skipped * * @sf: SPI flash to write to * @entry: Position and size of MRC cache in SPI flash @@ -48,4 +48,4 @@ struct mrc_data_container *mrccache_find_current(struct fmap_entry *entry); int mrccache_update(struct udevice *sf, struct fmap_entry *entry, struct mrc_data_container *cur); -#endif +#endif /* _ASM_MRCCACHE_H */ diff --git a/arch/x86/lib/mrccache.c b/arch/x86/lib/mrccache.c index 6dd3b5e..1c4b5a8 100644 --- a/arch/x86/lib/mrccache.c +++ b/arch/x86/lib/mrccache.c @@ -1,5 +1,5 @@ /* - * From Coreboot src/southbridge/intel/bd82x6x/mrccache.c + * From coreboot src/southbridge/intel/bd82x6x/mrccache.c * * Copyright (C) 2014 Google Inc. * @@ -15,17 +15,19 @@ #include <asm/mrccache.h> static struct mrc_data_container *next_mrc_block( - struct mrc_data_container *mrc_cache) + struct mrc_data_container *cache) { /* MRC data blocks are aligned within the region */ - u32 mrc_size = sizeof(*mrc_cache) + mrc_cache->data_size; + u32 mrc_size = sizeof(*cache) + cache->data_size; + u8 *region_ptr = (u8 *)cache; + if (mrc_size & (MRC_DATA_ALIGN - 1UL)) { mrc_size &= ~(MRC_DATA_ALIGN - 1UL); mrc_size += MRC_DATA_ALIGN; } - u8 *region_ptr = (u8 *)mrc_cache; region_ptr += mrc_size; + return (struct mrc_data_container *)region_ptr; } @@ -34,10 +36,6 @@ static int is_mrc_cache(struct mrc_data_container *cache) return cache && (cache->signature == MRC_DATA_SIGNATURE); } -/* - * Find the largest index block in the MRC cache. Return NULL if none is - * found. - */ struct mrc_data_container *mrccache_find_current(struct fmap_entry *entry) { struct mrc_data_container *cache, *next; |