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| author | Bin Meng <bmeng.cn@gmail.com> | 2016-06-08 12:07:35 (GMT) |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2016-06-12 04:19:35 (GMT) |
| commit | f7a01e4848a97935985f58e5cd1b133dad298323 (patch) | |
| tree | 1c7612486a056800694dd6784bda67ba03a1b9f3 /arch/x86 | |
| parent | 58d1fedb1f7d1a65918dcdc82c53f83b4c813368 (diff) | |
| download | u-boot-f7a01e4848a97935985f58e5cd1b133dad298323.tar.xz | |
x86: baytrail: Configure card detect pin of the SD controller
As of today, the latest version FSP (gold4) for BayTrail misses the
PAD configuration of the SD controller's Card Detect signal. The
default PAD value for the CD pin sets the pin to work in GPIO mode,
which causes card detect status cannot be reflected by the Present
State register in the SD controller (bit 16 & bit 18 are always zero).
Add a configuration for this pin in the pinctrl node.
Note I've checked the PAD configuration for all the pins in all the
3 controllers (eMMC/SDIO/SD). Only this SDMMC3_CD_B pin does not get
initialized to correct mode by FSP. With fsp,emmc-boot-mode set to
2 (eMMC 4.1), eMMC pins are initialized to func 1, but if we set
fsp,emmc-boot-mode to 1 (auto), those pins are initialized to func 3
which is correct according to datasheet.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86')
| -rw-r--r-- | arch/x86/dts/bayleybay.dts | 15 | ||||
| -rw-r--r-- | arch/x86/dts/conga-qeval20-qa3-e3845.dts | 15 | ||||
| -rw-r--r-- | arch/x86/dts/minnowmax.dts | 15 |
3 files changed, 45 insertions, 0 deletions
diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts index 1c2f671..c8907ce 100644 --- a/arch/x86/dts/bayleybay.dts +++ b/arch/x86/dts/bayleybay.dts @@ -68,6 +68,21 @@ pch_pinctrl { compatible = "intel,x86-pinctrl"; reg = <0 0>; + + /* + * As of today, the latest version FSP (gold4) for BayTrail + * misses the PAD configuration of the SD controller's Card + * Detect signal. The default PAD value for the CD pin sets + * the pin to work in GPIO mode, which causes card detect + * status cannot be reflected by the Present State register + * in the SD controller (bit 16 & bit 18 are always zero). + * + * Configure this pin to function 1 (SD controller). + */ + sdmmc3_cd@0 { + pad-offset = <0x3a0>; + mode-func = <1>; + }; }; pci { diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts b/arch/x86/dts/conga-qeval20-qa3-e3845.dts index 1e14c8b..fba089d 100644 --- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts +++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts @@ -31,6 +31,21 @@ pch_pinctrl { compatible = "intel,x86-pinctrl"; reg = <0 0>; + + /* + * As of today, the latest version FSP (gold4) for BayTrail + * misses the PAD configuration of the SD controller's Card + * Detect signal. The default PAD value for the CD pin sets + * the pin to work in GPIO mode, which causes card detect + * status cannot be reflected by the Present State register + * in the SD controller (bit 16 & bit 18 are always zero). + * + * Configure this pin to function 1 (SD controller). + */ + sdmmc3_cd@0 { + pad-offset = <0x3a0>; + mode-func = <1>; + }; }; chosen { diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index ba96e36..1a8a8cc 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -73,6 +73,21 @@ output-value = <1>; direction = <PIN_OUTPUT>; }; + + /* + * As of today, the latest version FSP (gold4) for BayTrail + * misses the PAD configuration of the SD controller's Card + * Detect signal. The default PAD value for the CD pin sets + * the pin to work in GPIO mode, which causes card detect + * status cannot be reflected by the Present State register + * in the SD controller (bit 16 & bit 18 are always zero). + * + * Configure this pin to function 1 (SD controller). + */ + sdmmc3_cd@0 { + pad-offset = <0x3a0>; + mode-func = <1>; + }; }; chosen { |