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| author | Chris Zankel <chris@zankel.net> | 2016-08-10 15:36:44 (GMT) |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-08-15 22:46:38 (GMT) |
| commit | c978b52410016b0ab5a213f235596340af8d45f7 (patch) | |
| tree | b01e9a8ea9a92fe962a545974339677b87dcc1ba /arch/xtensa/cpu/Makefile | |
| parent | de5e5cea022ab44006ff1edf45a39f0943fb9dff (diff) | |
| download | u-boot-c978b52410016b0ab5a213f235596340af8d45f7.tar.xz | |
xtensa: add support for the xtensa processor architecture [2/2]
The Xtensa processor architecture is a configurable, extensible,
and synthesizable 32-bit RISC processor core provided by Tensilica, inc.
This is the second part of the basic architecture port, adding the
'arch/xtensa' directory and a readme file.
Signed-off-by: Chris Zankel <chris@zankel.net>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/xtensa/cpu/Makefile')
| -rw-r--r-- | arch/xtensa/cpu/Makefile | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/xtensa/cpu/Makefile b/arch/xtensa/cpu/Makefile new file mode 100644 index 0000000..e83f620 --- /dev/null +++ b/arch/xtensa/cpu/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2007 - 2013 Tensilica, Inc. +# (C) Copyright 2014 - 2016 Cadence Design Systems Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y = cpu.o exceptions.o +extra-y = start.o |