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authorSimon Glass <sjg@chromium.org>2014-11-13 05:42:14 (GMT)
committerSimon Glass <sjg@chromium.org>2014-11-21 06:34:12 (GMT)
commit6fb3b72e8745073465b4a5875b7750cc43cbd1af (patch)
treee4a798cc0d1a9741752d0b4adde393d1d4d1e936 /arch
parent6e5b12b6144acd83dcfb4a79ea0beff787f3f545 (diff)
downloadu-boot-6fb3b72e8745073465b4a5875b7750cc43cbd1af.tar.xz
x86: pci: Allow configuration before relocation
Add simple PCI access routines for x86 which permit use before relocation. The normal PCI stack is still used, but for pre-relocation use there can only ever be a single hose. After relocation, fall back to the normal access, although even then on x86 machines there is normally only a single PCI bus. Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/x86/cpu/pci.c50
-rw-r--r--arch/x86/include/asm/pci.h13
2 files changed, 63 insertions, 0 deletions
diff --git a/arch/x86/cpu/pci.c b/arch/x86/cpu/pci.c
index 2d8f16c..e399388 100644
--- a/arch/x86/cpu/pci.c
+++ b/arch/x86/cpu/pci.c
@@ -46,3 +46,53 @@ void pci_init_board(void)
hose->last_busno = pci_hose_scan(hose);
}
+
+static struct pci_controller *get_hose(void)
+{
+ if (gd->arch.hose)
+ return gd->arch.hose;
+
+ return pci_bus_to_hose(0);
+}
+
+unsigned int pci_read_config8(pci_dev_t dev, unsigned where)
+{
+ uint8_t value;
+
+ pci_hose_read_config_byte(get_hose(), dev, where, &value);
+
+ return value;
+}
+
+unsigned int pci_read_config16(pci_dev_t dev, unsigned where)
+{
+ uint16_t value;
+
+ pci_hose_read_config_word(get_hose(), dev, where, &value);
+
+ return value;
+}
+
+unsigned int pci_read_config32(pci_dev_t dev, unsigned where)
+{
+ uint32_t value;
+
+ pci_hose_read_config_dword(get_hose(), dev, where, &value);
+
+ return value;
+}
+
+void pci_write_config8(pci_dev_t dev, unsigned where, unsigned value)
+{
+ pci_hose_write_config_byte(get_hose(), dev, where, value);
+}
+
+void pci_write_config16(pci_dev_t dev, unsigned where, unsigned value)
+{
+ pci_hose_write_config_word(get_hose(), dev, where, value);
+}
+
+void pci_write_config32(pci_dev_t dev, unsigned where, unsigned value)
+{
+ pci_hose_write_config_dword(get_hose(), dev, where, value);
+}
diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h
index 6e70a99..98817aa 100644
--- a/arch/x86/include/asm/pci.h
+++ b/arch/x86/include/asm/pci.h
@@ -33,4 +33,17 @@ void board_pci_setup_hose(struct pci_controller *hose);
* later use, but will become invalid one DRAM is available.
*/
int pci_early_init_hose(struct pci_controller **hosep);
+
+/*
+ * Simple PCI access routines - these work from either the early PCI hose
+ * or the 'real' one, created after U-Boot has memory available
+ */
+unsigned int pci_read_config8(pci_dev_t dev, unsigned where);
+unsigned int pci_read_config16(pci_dev_t dev, unsigned where);
+unsigned int pci_read_config32(pci_dev_t dev, unsigned where);
+
+void pci_write_config8(pci_dev_t dev, unsigned where, unsigned value);
+void pci_write_config16(pci_dev_t dev, unsigned where, unsigned value);
+void pci_write_config32(pci_dev_t dev, unsigned where, unsigned value);
+
#endif