diff options
author | Sylvain Lemieux <slemieux@tycoint.com> | 2015-07-27 17:37:34 (GMT) |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2015-08-17 12:10:53 (GMT) |
commit | d75b532a9e81a918852a3378e769d07dbfd59f15 (patch) | |
tree | c8bc2fd387032b8a5c48318d2c88a0d04bbaeca3 /arch | |
parent | f0b38f2a41945b2bae2209f791e66500f3726c36 (diff) | |
download | u-boot-d75b532a9e81a918852a3378e769d07dbfd59f15.tar.xz |
arm: lpc32xx: mux: add missing registers
Add missing registers in struct definition.
Update GPIO MUX base register to match GPIO base (refer to "LPC32x0 User manual" Rev. 3 - 22 July 2011).
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/include/asm/arch-lpc32xx/cpu.h | 2 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-lpc32xx/mux.h | 17 |
2 files changed, 18 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-lpc32xx/cpu.h b/arch/arm/include/asm/arch-lpc32xx/cpu.h index 0b5dca1..0de894b 100644 --- a/arch/arm/include/asm/arch-lpc32xx/cpu.h +++ b/arch/arm/include/asm/arch-lpc32xx/cpu.h @@ -27,7 +27,7 @@ #define HS_UART7_BASE 0x4001C000 /* High speed UART 7 registers base */ #define RTC_BASE 0x40024000 /* RTC registers base */ #define GPIO_BASE 0x40028000 /* GPIO registers base */ -#define MUX_BASE 0x40028100 /* MUX registers base */ +#define MUX_BASE 0x40028000 /* MUX registers base */ #define WDT_BASE 0x4003C000 /* Watchdog timer registers base */ #define TIMER0_BASE 0x40044000 /* Timer0 registers base */ #define TIMER1_BASE 0x4004C000 /* Timer1 registers base */ diff --git a/arch/arm/include/asm/arch-lpc32xx/mux.h b/arch/arm/include/asm/arch-lpc32xx/mux.h index dc1b5bc..665ea3f 100644 --- a/arch/arm/include/asm/arch-lpc32xx/mux.h +++ b/arch/arm/include/asm/arch-lpc32xx/mux.h @@ -12,7 +12,24 @@ */ struct mux_regs { + u32 reserved1[10]; + u32 p2_mux_set; + u32 p2_mux_clr; + u32 p2_mux_state; + u32 reserved2[51]; u32 p_mux_set; u32 p_mux_clr; u32 p_mux_state; + u32 reserved3; + u32 p3_mux_set; + u32 p3_mux_clr; + u32 p3_mux_state; + u32 reserved4; + u32 p0_mux_set; + u32 p0_mux_clr; + u32 p0_mux_state; + u32 reserved5; + u32 p1_mux_set; + u32 p1_mux_clr; + u32 p1_mux_state; }; |