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authorPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>2017-08-30 09:54:05 (GMT)
committerPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>2017-08-30 09:54:05 (GMT)
commitde23ed62192579338359e37040701b35153d3d5e (patch)
treefde701176e4fb9866d96a5816e80c055c70a679b /arch
parent12b9315fb9e410662bb745c1e2495ef7e7b977f0 (diff)
downloadu-boot-de23ed62192579338359e37040701b35153d3d5e.tar.xz
board: common: vid: Add support for LTC3882 voltage regulator chip
Restructures common driver to support LTC3882 voltage regulator chip. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h9
1 files changed, 7 insertions, 2 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index fec8fcd..d48484a 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -197,10 +197,15 @@ struct ccsr_gur {
u32 gpporcr3;
u32 gpporcr4;
u8 res_030[0x60-0x30];
-#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 2
#define FSL_CHASSIS3_DCFG_FUSESR_VID_MASK 0x1F
-#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 7
#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK 0x1F
+#if defined(CONFIG_ARCH_LS1088A)
+#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 25
+#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 20
+#else
+#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 2
+#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 7
+#endif
u32 dcfg_fusesr; /* Fuse status register */
u8 res_064[0x70-0x64];
u32 devdisr; /* Device disable control 1 */