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authorTom Rini <trini@konsulko.com>2017-09-20 16:32:34 (GMT)
committerTom Rini <trini@konsulko.com>2017-09-20 16:32:34 (GMT)
commite884656c2c0b2406b9bf99ea76f5a8c75128a331 (patch)
tree520d14bd1fdaed0adefc4209f53dc0d0d1467b67 /arch
parent975f97b43181694041f77ecd8118364afe588144 (diff)
parent031426a7af63d3c939fc963311e6dc8e904a0440 (diff)
downloadu-boot-e884656c2c0b2406b9bf99ea76f5a8c75128a331.tar.xz
Merge git://www.denx.de/git/u-boot-imx
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/include/asm/arch-mx6/sys_proto.h7
-rw-r--r--arch/arm/include/asm/arch-mx7/clock.h6
-rw-r--r--arch/arm/mach-imx/mx7/clock.c6
-rw-r--r--arch/arm/mach-imx/spl.c22
4 files changed, 35 insertions, 6 deletions
diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h
index 14f5d94..ba73943 100644
--- a/arch/arm/include/asm/arch-mx6/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx6/sys_proto.h
@@ -6,3 +6,10 @@
*/
#include <asm/mach-imx/sys_proto.h>
+
+#define USBPHY_PWD 0x00000000
+
+#define USBPHY_PWD_RXPWDRX (1 << 20) /* receiver block power down */
+
+#define is_usbotg_phy_active(void) (!(readl(USB_PHY0_BASE_ADDR + USBPHY_PWD) & \
+ USBPHY_PWD_RXPWDRX))
diff --git a/arch/arm/include/asm/arch-mx7/clock.h b/arch/arm/include/asm/arch-mx7/clock.h
index 688d236..3b115ad 100644
--- a/arch/arm/include/asm/arch-mx7/clock.h
+++ b/arch/arm/include/asm/arch-mx7/clock.h
@@ -318,9 +318,9 @@ struct clk_root_map {
};
enum enet_freq {
- ENET_25MHz,
- ENET_50MHz,
- ENET_125MHz,
+ ENET_25MHZ,
+ ENET_50MHZ,
+ ENET_125MHZ,
};
u32 get_root_clk(enum clk_root_index clock_id);
diff --git a/arch/arm/mach-imx/mx7/clock.c b/arch/arm/mach-imx/mx7/clock.c
index 2cfde46..8150faa 100644
--- a/arch/arm/mach-imx/mx7/clock.c
+++ b/arch/arm/mach-imx/mx7/clock.c
@@ -966,15 +966,15 @@ int set_clk_enet(enum enet_freq type)
clock_enable(CCGR_ENET2, 0);
switch (type) {
- case ENET_125MHz:
+ case ENET_125MHZ:
enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
break;
- case ENET_50MHz:
+ case ENET_50MHZ:
enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
break;
- case ENET_25MHz:
+ case ENET_25MHZ:
enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
break;
diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c
index 258578a..5944f99 100644
--- a/arch/arm/mach-imx/spl.c
+++ b/arch/arm/mach-imx/spl.c
@@ -14,6 +14,7 @@
#include <asm/spl.h>
#include <spl.h>
#include <asm/mach-imx/hab.h>
+#include <g_dnl.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -31,6 +32,18 @@ u32 spl_boot_device(void)
if (((bmode >> 24) & 0x03) == 0x01) /* Serial Downloader */
return BOOT_DEVICE_BOARD;
+ /*
+ * The above method does not detect that the boot ROM used
+ * serial downloader in case the boot ROM decided to use the
+ * serial downloader as a fall back (primary boot source failed).
+ *
+ * Infer that the boot ROM used the USB serial downloader by
+ * checking whether the USB PHY is currently active... This
+ * assumes that SPL did not (yet) initialize the USB PHY...
+ */
+ if (is_usbotg_phy_active())
+ return BOOT_DEVICE_BOARD;
+
/* BOOT_CFG1[7:4] - see IMX6DQRM Table 8-8 */
switch ((reg & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
/* EIM: See 8.5.1, Table 8-9 */
@@ -82,6 +95,15 @@ u32 spl_boot_device(void)
}
return BOOT_DEVICE_NONE;
}
+
+#ifdef CONFIG_SPL_USB_GADGET_SUPPORT
+int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
+{
+ put_unaligned(CONFIG_G_DNL_PRODUCT_NUM + 0xfff, &dev->idProduct);
+
+ return 0;
+}
+#endif
#endif
#if defined(CONFIG_SPL_MMC_SUPPORT)