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authorSimon Glass <sjg@chromium.org>2017-03-31 14:40:25 (GMT)
committerTom Rini <trini@konsulko.com>2017-04-05 17:59:20 (GMT)
commit088454cde245b4d431ce0181be8b3cbceea059d6 (patch)
treeec86ebe66961c9b06ab4b39ec83fd81d4a86e9be /arch
parent52c411805c090999f015df8bdf8016fb684746d0 (diff)
downloadu-boot-088454cde245b4d431ce0181be8b3cbceea059d6.tar.xz
board_f: Drop return value from initdram()
At present we cannot use this function as an init sequence call without a wrapper, since it returns the RAM size. Adjust it to set the RAM size in global_data instead, and return 0 on success. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/cpu.c2
-rw-r--r--arch/mips/mach-ath79/dram.c8
-rw-r--r--arch/mips/mach-pic32/cpu.c6
-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu.c14
-rw-r--r--arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c18
-rw-r--r--arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c8
-rw-r--r--arch/powerpc/cpu/ppc4xx/sdram.c18
7 files changed, 51 insertions, 23 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index d260e5d..1e6d90c 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -874,7 +874,7 @@ void update_early_mmu_table(void)
__weak int dram_init(void)
{
- gd->ram_size = initdram();
+ initdram();
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
/* This will break-before-make MMU for DDR */
update_early_mmu_table();
diff --git a/arch/mips/mach-ath79/dram.c b/arch/mips/mach-ath79/dram.c
index 5ef43a0..1c73add 100644
--- a/arch/mips/mach-ath79/dram.c
+++ b/arch/mips/mach-ath79/dram.c
@@ -9,8 +9,12 @@
#include <asm/addrspace.h>
#include <mach/ddr.h>
-phys_size_t initdram(void)
+DECLARE_GLOBAL_DATA_PTR;
+
+int initdram(void)
{
ddr_tap_tuning();
- return get_ram_size((void *)KSEG1, SZ_256M);
+ gd->ram_size = get_ram_size((void *)KSEG1, SZ_256M);
+
+ return 0;
}
diff --git a/arch/mips/mach-pic32/cpu.c b/arch/mips/mach-pic32/cpu.c
index f15b58d..c96e046 100644
--- a/arch/mips/mach-pic32/cpu.c
+++ b/arch/mips/mach-pic32/cpu.c
@@ -110,12 +110,14 @@ static void ddr2_pmd_ungate(void)
}
/* initialize the DDR2 Controller and DDR2 PHY */
-phys_size_t initdram(void)
+int initdram(void)
{
ddr2_pmd_ungate();
ddr2_phy_init();
ddr2_ctrl_init();
- return ddr2_calculate_size();
+ gd->ram_size = ddr2_calculate_size();
+
+ return 0;
}
int misc_init_r(void)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 192634d..64e0aa7 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -401,17 +401,19 @@ void mpc85xx_reginfo(void)
#ifndef CONFIG_FSL_CORENET
#if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
!defined(CONFIG_SYS_INIT_L2_ADDR)
-phys_size_t initdram(void)
+int initdram(void)
{
#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \
defined(CONFIG_ARCH_QEMU_E500)
- return fsl_ddr_sdram_size();
+ gd->ram_size = fsl_ddr_sdram_size();
#else
- return (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+ gd->ram_size = (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
#endif
+
+ return 0;
}
#else /* CONFIG_SYS_RAMBOOT */
-phys_size_t initdram(void)
+int initdram(void)
{
phys_size_t dram_size = 0;
@@ -460,7 +462,9 @@ phys_size_t initdram(void)
#endif
debug("DDR: ");
- return dram_size;
+ gd->ram_size = dram_size;
+
+ return 0;
}
#endif /* CONFIG_SYS_RAMBOOT */
#endif
diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
index 3b79efb..87fd5e6 100644
--- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
@@ -33,6 +33,8 @@
#include "ecc.h"
+DECLARE_GLOBAL_DATA_PTR;
+
#define PPC4xx_IBM_DDR2_DUMP_REGISTER(mnemonic) \
do { \
u32 data; \
@@ -414,7 +416,7 @@ static unsigned char spd_read(uchar chip, uint addr)
* banks appropriately. If Auto Memory Configuration is
* not used, it is assumed that no DIMM is plugged
*-----------------------------------------------------------------------------*/
-phys_size_t initdram(void)
+int initdram(void)
{
unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
unsigned long dimm_populated[MAXDIMMS] = {SDRAM_NONE, SDRAM_NONE};
@@ -429,7 +431,9 @@ phys_size_t initdram(void)
* Reduce RAM size to avoid overwriting memory used by
* current stack? Not sure what is happening.
*/
- return sdram_memsize() / 2;
+ gd->ram_size = sdram_memsize() / 2;
+
+ return 0;
}
num_dimm_banks = sizeof(iic0_dimm_addr);
@@ -650,7 +654,9 @@ phys_size_t initdram(void)
*/
set_mcsr(get_mcsr());
- return sdram_memsize();
+ gd->ram_size = sdram_memsize();
+
+ return 0;
}
static void get_spd_info(unsigned long *dimm_populated,
@@ -2855,7 +2861,7 @@ static void test(void)
* time parameters.
* Configures the PPC405EX(r) and PPC460EX/GT
*---------------------------------------------------------------------------*/
-phys_size_t initdram(void)
+int initdram(void)
{
unsigned long val;
@@ -3011,7 +3017,9 @@ phys_size_t initdram(void)
set_mcsr(get_mcsr());
#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
- return (CONFIG_SYS_MBYTES_SDRAM << 20);
+ gd->ram_size = CONFIG_SYS_MBYTES_SDRAM << 20;
+
+ return 0;
}
#endif /* CONFIG_SPD_EEPROM */
diff --git a/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c
index 3b072b7..14d0fd9 100644
--- a/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c
+++ b/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c
@@ -30,6 +30,8 @@
#include <asm/mmu.h>
#include <asm/cache.h>
+DECLARE_GLOBAL_DATA_PTR;
+
#if defined(CONFIG_SPD_EEPROM) && \
(defined(CONFIG_440EPX) || defined(CONFIG_440GRX))
@@ -998,7 +1000,7 @@ static void program_ddr0_44(unsigned long dimm_ranks[],
* banks appropriately. If Auto Memory Configuration is
* not used, it is assumed that no DIMM is plugged
*-----------------------------------------------------------------------------*/
-phys_size_t initdram(void)
+int initdram(void)
{
unsigned char const iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
unsigned long dimm_ranks[MAXDIMMS];
@@ -1212,7 +1214,9 @@ phys_size_t initdram(void)
#endif /* defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC) */
program_tlb(0, CONFIG_SYS_SDRAM_BASE, dram_size, MY_TLB_WORD2_I_ENABLE);
- return dram_size;
+ gd->ram_size = dram_size;
+
+ return 0;
}
void board_add_ram_info(int use_default)
diff --git a/arch/powerpc/cpu/ppc4xx/sdram.c b/arch/powerpc/cpu/ppc4xx/sdram.c
index 2d80571..a49bd69 100644
--- a/arch/powerpc/cpu/ppc4xx/sdram.c
+++ b/arch/powerpc/cpu/ppc4xx/sdram.c
@@ -17,6 +17,8 @@
#include "sdram.h"
#include "ecc.h"
+DECLARE_GLOBAL_DATA_PTR;
+
#ifdef CONFIG_SDRAM_BANK0
#ifndef CONFIG_440
@@ -148,7 +150,7 @@ static ulong compute_rtr(ulong speed, ulong rows, ulong refresh)
/*
* Autodetect onboard SDRAM on 405 platforms
*/
-phys_size_t initdram(void)
+int initdram(void)
{
ulong speed;
ulong sdtr1;
@@ -226,11 +228,13 @@ phys_size_t initdram(void)
/*
* OK, size detected -> all done
*/
- return size;
+ gd->ram_size = size;
+
+ return 0;
}
}
- return 0;
+ return -ENXIO;
}
#else /* CONFIG_440 */
@@ -349,7 +353,7 @@ static void sdram_tr1_set(int ram_address, int* tr1_value)
* so this should be extended for other future boards
* using this routine!
*/
-phys_size_t initdram(void)
+int initdram(void)
{
int i;
int tr1_bank1;
@@ -440,11 +444,13 @@ phys_size_t initdram(void)
/*
* OK, size detected -> all done
*/
- return size;
+ gd->ram_size = size;
+
+ return 0;
}
}
- return 0; /* nothing found ! */
+ return -ENXIO; /* nothing found ! */
}
#endif /* CONFIG_440 */