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authorTom Rini <trini@konsulko.com>2016-09-22 15:36:23 (GMT)
committerTom Rini <trini@konsulko.com>2016-09-22 15:36:23 (GMT)
commit58c8c0963b1c720802c46ac4288c897e5f9cd296 (patch)
tree08458bac1c2339713a4e0721ff857bcf123aecd6 /arch
parenta6c1309782e7a4a6b18e9514ca927487b5727232 (diff)
parente0027f089bb64f6b84742c580f966bf9c97c900e (diff)
downloadu-boot-58c8c0963b1c720802c46ac4288c897e5f9cd296.tar.xz
Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/cpu/armv8/zynqmp/Kconfig48
-rw-r--r--arch/arm/cpu/armv8/zynqmp/spl.c30
-rw-r--r--arch/arm/include/asm/arch-zynqmp/hardware.h14
-rw-r--r--arch/arm/include/asm/spl.h1
4 files changed, 92 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig b/arch/arm/cpu/armv8/zynqmp/Kconfig
index e703991..1eedb39 100644
--- a/arch/arm/cpu/armv8/zynqmp/Kconfig
+++ b/arch/arm/cpu/armv8/zynqmp/Kconfig
@@ -47,5 +47,53 @@ config ZYNQMP_USB
config SYS_MALLOC_F_LEN
default 0x600
+config SPL_ZYNQMP_ALT_BOOTMODE_ENABLED
+ bool "Overwrite SPL bootmode"
+ depends on SPL
+ help
+ Overwrite bootmode selected via boot mode pins to tell SPL what should
+ be the next boot device.
+
+config SPL_ZYNQMP_ALT_BOOTMODE
+ hex
+ default 0x0 if JTAG_MODE
+ default 0x1 if QSPI_MODE_24BIT
+ default 0x2 if QSPI_MODE_32BIT
+ default 0x3 if SD_MODE
+ default 0x4 if NAND_MODE
+ default 0x5 if SD_MODE1
+ default 0x6 if EMMC_MODE
+ default 0x7 if USB_MODE
+
+choice
+ prompt "Boot mode"
+ depends on ZYNQMP_ALT_BOOTMODE_ENABLED
+ default JTAG
+
+config JTAG_MODE
+ bool "JTAG_MODE"
+
+config QSPI_MODE_24BIT
+ bool "QSPI_MODE_24BIT"
+
+config QSPI_MODE_32BIT
+ bool "QSPI_MODE_32BIT"
+
+config SD_MODE
+ bool "SD_MODE"
+
+config SD_MODE1
+ bool "SD_MODE1"
+
+config NAND_MODE
+ bool "NAND_MODE"
+
+config EMMC_MODE
+ bool "EMMC_MODE"
+
+config USB_MODE
+ bool "USB"
+
+endchoice
endif
diff --git a/arch/arm/cpu/armv8/zynqmp/spl.c b/arch/arm/cpu/armv8/zynqmp/spl.c
index 867d2b2..04e1905 100644
--- a/arch/arm/cpu/armv8/zynqmp/spl.c
+++ b/arch/arm/cpu/armv8/zynqmp/spl.c
@@ -35,10 +35,29 @@ void board_init_f(ulong dummy)
board_init_r(NULL, 0);
}
+static void ps_mode_reset(ulong mode)
+{
+ writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT,
+ &crlapb_base->boot_pin_ctrl);
+ udelay(5);
+ writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT |
+ mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT,
+ &crlapb_base->boot_pin_ctrl);
+}
+
+/*
+ * Set default PS_MODE1 which is used for USB ULPI phy reset
+ * Also other resets can be connected to this certain pin
+ */
+#ifndef MODE_RESET
+# define MODE_RESET PS_MODE1
+#endif
+
#ifdef CONFIG_SPL_BOARD_INIT
void spl_board_init(void)
{
preloader_console_init();
+ ps_mode_reset(MODE_RESET);
board_init();
}
#endif
@@ -48,6 +67,13 @@ u32 spl_boot_device(void)
u32 reg = 0;
u8 bootmode;
+#if defined(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE_ENABLED)
+ /* Change default boot mode at run-time */
+ writel(BOOT_MODE_USE_ALT |
+ CONFIG_SPL_ZYNQMP_ALT_BOOTMODE << BOOT_MODE_ALT_SHIFT,
+ &crlapb_base->boot_mode);
+#endif
+
reg = readl(&crlapb_base->boot_mode);
bootmode = reg & BOOT_MODES_MASK;
@@ -60,6 +86,10 @@ u32 spl_boot_device(void)
case SD_MODE1:
return BOOT_DEVICE_MMC1;
#endif
+#ifdef CONFIG_SPL_DFU_SUPPORT
+ case USB_MODE:
+ return BOOT_DEVICE_DFU;
+#endif
default:
printf("Invalid Boot Mode:0x%x\n", bootmode);
break;
diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h
index 35964d6..456c1b0 100644
--- a/arch/arm/include/asm/arch-zynqmp/hardware.h
+++ b/arch/arm/include/asm/arch-zynqmp/hardware.h
@@ -25,6 +25,13 @@
#define ZYNQMP_CRL_APB_BASEADDR 0xFF5E0000
#define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1000000
+#define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT 0
+#define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT 8
+
+#define PS_MODE0 BIT(0)
+#define PS_MODE1 BIT(1)
+#define PS_MODE2 BIT(2)
+#define PS_MODE3 BIT(3)
struct crlapb_regs {
u32 reserved0[36];
@@ -35,7 +42,9 @@ struct crlapb_regs {
u32 boot_mode; /* 0x200 */
u32 reserved3[14];
u32 rst_lpd_top; /* 0x23C */
- u32 reserved4[26];
+ u32 reserved4[4];
+ u32 boot_pin_ctrl; /* 0x250 */
+ u32 reserved5[21];
};
#define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR)
@@ -69,7 +78,10 @@ struct iou_scntr_secure {
#define SD_MODE1 0x00000005 /* sd 1 */
#define NAND_MODE 0x00000004
#define EMMC_MODE 0x00000006
+#define USB_MODE 0x00000007
#define JTAG_MODE 0x00000000
+#define BOOT_MODE_USE_ALT 0x100
+#define BOOT_MODE_ALT_SHIFT 12
#define ZYNQMP_IOU_SLCR_BASEADDR 0xFF180000
diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h
index 19c38f4..6f312d6 100644
--- a/arch/arm/include/asm/spl.h
+++ b/arch/arm/include/asm/spl.h
@@ -28,6 +28,7 @@ enum {
BOOT_DEVICE_SATA,
BOOT_DEVICE_I2C,
BOOT_DEVICE_BOARD,
+ BOOT_DEVICE_DFU,
BOOT_DEVICE_NONE
};
#endif