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| author | Philipp Tomsich <philipp.tomsich@theobroma-systems.com> | 2017-07-28 09:37:33 (GMT) |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@theobroma-systems.com> | 2017-08-13 15:12:23 (GMT) |
| commit | 8f362dbb41b6857c5ee18e82e74d19c7a1110278 (patch) | |
| tree | 5108daa23dd9adcd75eb7706f3cfc4c5a03960b0 /arch | |
| parent | c1828cf7abaae7283e48bb857283936fdaf2ef72 (diff) | |
| download | u-boot-8f362dbb41b6857c5ee18e82e74d19c7a1110278.tar.xz | |
rockchip: rk3368: dts: add sgrf node
We will to drop device security temporarily (until the ATF initialises
it fully) from the TPL/SPL stage: this requires access to some
registers in the SGRF.
This adds the sgrf node to the rk3368.dtsi, so we can then bind a
syscon device onto it and access its memory ranges.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/dts/rk3368.dtsi | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/dts/rk3368.dtsi b/arch/arm/dts/rk3368.dtsi index 9daf765..59c20da 100644 --- a/arch/arm/dts/rk3368.dtsi +++ b/arch/arm/dts/rk3368.dtsi @@ -652,6 +652,11 @@ reg = <0x0 0xff738000 0x0 0x1000>; }; + sgrf: syscon@ff740000 { + compatible = "rockchip,rk3368-sgrf", "syscon"; + reg = <0x0 0xff740000 0x0 0x1000>; + }; + cru: clock-controller@ff760000 { compatible = "rockchip,rk3368-cru"; reg = <0x0 0xff760000 0x0 0x1000>; |