diff options
| author | Hadli, Manjunath <manjunath.hadli@ti.com> | 2012-02-06 00:30:44 (GMT) |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-02-12 09:11:32 (GMT) |
| commit | 8f5d468721ef3931e4c6f9c6555348f26acdec19 (patch) | |
| tree | 991231570cd059ac3c5dd545648c0619421aa01e /arch | |
| parent | 6678cebc09226f9d34fb7e5e0631d0009689918b (diff) | |
| download | u-boot-8f5d468721ef3931e4c6f9c6555348f26acdec19.tar.xz | |
davinci: add support for printing clock frequency
add support for printing various clock frequency info found
in SOC such as ARM core frequency, DSP core frequency and DDR
frequency as part of bdinfo command.
Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com>
Cc: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/cpu/arm926ejs/davinci/cpu.c | 32 | ||||
| -rw-r--r-- | arch/arm/include/asm/u-boot.h | 3 | ||||
| -rw-r--r-- | arch/arm/lib/board.c | 10 |
3 files changed, 44 insertions, 1 deletions
diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c b/arch/arm/cpu/arm926ejs/davinci/cpu.c index 1735555..b3c9fb7 100644 --- a/arch/arm/cpu/arm926ejs/davinci/cpu.c +++ b/arch/arm/cpu/arm926ejs/davinci/cpu.c @@ -25,6 +25,8 @@ #include <asm/arch/hardware.h> #include <asm/io.h> +DECLARE_GLOBAL_DATA_PTR; + /* offsets from PLL controller base */ #define PLLC_PLLCTL 0x100 #define PLLC_PLLM 0x110 @@ -187,6 +189,36 @@ unsigned int davinci_clk_get(unsigned int div) #endif #endif /* !CONFIG_SOC_DA8XX */ +int set_cpu_clk_info(void) +{ +#ifdef CONFIG_SOC_DA8XX + gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000; + /* DDR PHY uses an x2 input clock */ + gd->bd->bi_ddr_freq = clk_get(0x10001) / 1000000; +#else + + unsigned int pllbase = DAVINCI_PLL_CNTRL0_BASE; +#if defined(CONFIG_SOC_DM365) + pllbase = DAVINCI_PLL_CNTRL1_BASE; +#endif + gd->bd->bi_arm_freq = pll_sysclk_mhz(pllbase, ARM_PLLDIV); + +#ifdef DSP_PLLDIV + gd->bd->bi_dsp_freq = + pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DSP_PLLDIV); +#else + gd->bd->bi_dsp_freq = 0; +#endif + + pllbase = DAVINCI_PLL_CNTRL1_BASE; +#if defined(CONFIG_SOC_DM365) + pllbase = DAVINCI_PLL_CNTRL0_BASE; +#endif + gd->bd->bi_ddr_freq = pll_sysclk_mhz(pllbase, DDR_PLLDIV) / 2; +#endif + return 0; +} + /* * Initializes on-chip ethernet controllers. * to override, implement board_eth_init() diff --git a/arch/arm/include/asm/u-boot.h b/arch/arm/include/asm/u-boot.h index f30b9fc..20e1653 100644 --- a/arch/arm/include/asm/u-boot.h +++ b/arch/arm/include/asm/u-boot.h @@ -41,6 +41,9 @@ typedef struct bd_info { unsigned long bi_ip_addr; /* IP Address */ ulong bi_arch_number; /* unique id for this board */ ulong bi_boot_params; /* where this board expects params */ + unsigned long bi_arm_freq; /* arm frequency */ + unsigned long bi_dsp_freq; /* dsp core frequency */ + unsigned long bi_ddr_freq; /* ddr frequency */ struct /* RAM configuration */ { ulong start; diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index 3d78274..500e216 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -463,7 +463,15 @@ void board_init_r(gd_t *id, ulong dest_addr) debug("monitor flash len: %08lX\n", monitor_flash_len); board_init(); /* Setup chipselects */ - + /* + * TODO: printing of the clock inforamtion of the board is now + * implemented as part of bdinfo command. Currently only support for + * davinci SOC's is added. Remove this check once all the board + * implement this. + */ +#ifdef CONFIG_CLOCKS + set_cpu_clk_info(); /* Setup clock information */ +#endif #ifdef CONFIG_SERIAL_MULTI serial_initialize(); #endif |