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| author | Chin Liang See <clsee@altera.com> | 2016-09-21 02:25:56 (GMT) |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2016-10-27 06:03:07 (GMT) |
| commit | 89a54abf1bd1a8a9ebbea9808199ec8ee3d902bd (patch) | |
| tree | 35830c1c2691e0a2058793a03ee78fc932d92229 /board/altera/cyclone5-socdk/qts/sdram_config.h | |
| parent | 5ac5861c4ba851b473e6a24940b412b397627d8d (diff) | |
| download | u-boot-89a54abf1bd1a8a9ebbea9808199ec8ee3d902bd.tar.xz | |
ddr: altera: Configuring SDRAM extra cycles timing parameters
To enable configuration of sdr.ctrlcfg.extratime1 register which enable
extra clocks for read to write command timing. This is critical to
ensure successful LPDDR2 interface
Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Diffstat (limited to 'board/altera/cyclone5-socdk/qts/sdram_config.h')
0 files changed, 0 insertions, 0 deletions