diff options
author | Stefan Roese <sr@denx.de> | 2008-03-05 11:31:53 (GMT) |
---|---|---|
committer | Stefan Roese <sr@denx.de> | 2008-03-15 06:28:05 (GMT) |
commit | 41712b4e8c95dff23354bcd620e1f9477160c190 (patch) | |
tree | c3800ca822f1717ed06bb269689a5d6af2a6e7e3 /board/amcc | |
parent | 2596f5b9d353ff3e4387a3325d05740f16958038 (diff) | |
download | u-boot-41712b4e8c95dff23354bcd620e1f9477160c190.tar.xz |
ppc4xx: Add USB OHCI support to AMCC Canyonlands 460EX eval board
This patch adds USB OHCI support to the Canyonlands board port. It also
enables EXT2 support.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/amcc')
-rw-r--r-- | board/amcc/canyonlands/canyonlands.c | 14 | ||||
-rw-r--r-- | board/amcc/canyonlands/init.S | 3 |
2 files changed, 17 insertions, 0 deletions
diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c index 3551429..36779f5 100644 --- a/board/amcc/canyonlands/canyonlands.c +++ b/board/amcc/canyonlands/canyonlands.c @@ -26,6 +26,7 @@ #include <asm/io.h> #include <asm/mmu.h> #include <asm/4xx_pcie.h> +#include <asm/gpio.h> extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ @@ -100,6 +101,19 @@ int board_early_init_f(void) mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */ + /* Setup PLB4-AHB bridge based on the system address map */ + mtdcr(AHB_TOP, 0x8000004B); + mtdcr(AHB_BOT, 0x8000004B); + + /* + * Configure USB-STP pins as alternate and not GPIO + * It seems to be neccessary to configure the STP pins as GPIO + * input at powerup (perhaps while USB reset is asserted). So + * we configure those pins to their "real" function now. + */ + gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); + gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); + return 0; } diff --git a/board/amcc/canyonlands/init.S b/board/amcc/canyonlands/init.S index b7cac23..bd4cab5 100644 --- a/board/amcc/canyonlands/init.S +++ b/board/amcc/canyonlands/init.S @@ -88,6 +88,9 @@ tlbtab: /* TLB-entry for Local Configuration registers => peripherals */ tlbentry(CFG_LOCAL_CONF_REGS, SZ_16M, CFG_LOCAL_CONF_REGS, 4, AC_R|AC_W|AC_X|SA_G|SA_I) + /* AHB: Internal USB Peripherals (USB, SATA) */ + tlbentry(CFG_AHB_BASE, SZ_1M, 0xbff00000, 4, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbtab_end #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) |