diff options
| author | Heiko Schocher <hs@denx.de> | 2017-06-27 14:49:14 (GMT) |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-07-03 21:35:28 (GMT) |
| commit | 98f705c9cefdfdba62c069821bbba10273a0a8ed (patch) | |
| tree | 48a56e8496a9b6f5bcf523916ace5445489d79c7 /board/esd | |
| parent | d4db3b86a5e090e21db710bedbbe3e50d4c56428 (diff) | |
| download | u-boot-98f705c9cefdfdba62c069821bbba10273a0a8ed.tar.xz | |
powerpc: remove 4xx support
There was for long time no activity in the 4xx area.
We need to go further and convert to Kconfig, but it
turned out, nobody is interested anymore in 4xx,
so remove it.
Signed-off-by: Heiko Schocher <hs@denx.de>
Diffstat (limited to 'board/esd')
58 files changed, 0 insertions, 12969 deletions
diff --git a/board/esd/common/cmd_loadpci.c b/board/esd/common/cmd_loadpci.c deleted file mode 100644 index 9541817..0000000 --- a/board/esd/common/cmd_loadpci.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - * (C) Copyright 2005-2008 - * Matthias Fuchs, esd GmbH Germany, matthias.fuchs@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <console.h> -#if !defined(CONFIG_440) -#include <asm/4xx_pci.h> -#endif - -#if defined(CONFIG_CMD_BSP) -#define ADDRMASK 0xfffff000 - -/* - * Command loadpci: wait for signal from host and boot image. - */ -int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - u32 *ptr = 0; - int count = 0; - int count2 = 0; - char addr[16]; - char str[] = "\\|/-"; - u32 la, ptm1la; - -#if defined(CONFIG_440) - ptm1la = in32r(PCIL0_PTM1LA); -#else - ptm1la = in32r(PTM1LA); -#endif - while(1) { - /* - * Mark sync address - */ - ptr = (u32 *)ptm1la; - memset(ptr, 0, 0x20); - - *ptr = 0xffffffff; - puts("\nWaiting for action from pci host -"); - - /* - * Wait for host to write the start address - */ - while (*ptr == 0xffffffff) { - count++; - if (!(count % 100)) { - count2++; - putc(0x08); /* backspace */ - putc(str[count2 % 4]); - } - - /* Abort if ctrl-c was pressed */ - if (ctrlc()) { - puts("\nAbort\n"); - return 0; - } - - udelay(1000); - } - - printf("\nGot bootcode %08x: ", *ptr); - la = ptm1la + (*ptr & ADDRMASK); - sprintf(addr, "%08x", la); - - switch (*ptr & ~ADDRMASK) { - case 0: - /* - * Boot image via bootm - */ - printf("booting image at addr 0x%s ...\n", addr); - setenv("loadaddr", addr); - do_bootm(cmdtp, 0, 0, NULL); - break; - - case 1: - /* - * Boot image via "source" command - */ - printf("executing script at addr 0x%s ...\n", addr); - source(la, NULL); - break; - - case 2: - /* - * Call run_cmd - */ - printf("running command at addr 0x%s ...\n", addr); - run_command((char *)la, 0); - break; - - default: - printf("unhandled boot method\n"); - break; - } - } -} - -U_BOOT_CMD( - loadpci, 1, 1, do_loadpci, - "Wait for pci bootcmd and boot it", - "" -); - -#endif diff --git a/board/esd/common/esd405ep_nand.c b/board/esd/common/esd405ep_nand.c deleted file mode 100644 index 51ac10c..0000000 --- a/board/esd/common/esd405ep_nand.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - * (C) Copyright 2007 - * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> - -#if defined(CONFIG_CMD_NAND) -#include <asm/io.h> -#include <nand.h> - -/* - * hardware specific access to control-lines - */ -static void esd405ep_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) -{ - struct nand_chip *this = mtd_to_nand(mtd); - if (ctrl & NAND_CTRL_CHANGE) { - if ( ctrl & NAND_CLE ) - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_CLE); - else - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_NAND_CLE); - if ( ctrl & NAND_ALE ) - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_ALE); - else - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_NAND_ALE); - if ( ctrl & NAND_NCE ) - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_NAND_CE); - else - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_CE); - } - - if (cmd != NAND_CMD_NONE) - writeb(cmd, this->IO_ADDR_W); -} - - -/* - * read device ready pin - */ -static int esd405ep_nand_device_ready(struct mtd_info *mtdinfo) -{ - if (in_be32((void *)GPIO0_IR) & CONFIG_SYS_NAND_RDY) - return 1; - return 0; -} - - -int board_nand_init(struct nand_chip *nand) -{ - /* - * Set NAND-FLASH GPIO signals to defaults - */ - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE)); - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_CE); - - /* - * Initialize nand_chip structure - */ - nand->cmd_ctrl = esd405ep_nand_hwcontrol; - nand->dev_ready = esd405ep_nand_device_ready; - nand->ecc.mode = NAND_ECC_SOFT; - nand->chip_delay = NAND_BIG_DELAY_US; - nand->options = NAND_SAMSUNG_LP_OPTIONS; - return 0; -} -#endif diff --git a/board/esd/common/flash.c b/board/esd/common/flash.c deleted file mode 100644 index e3512c7..0000000 --- a/board/esd/common/flash.c +++ /dev/null @@ -1,659 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#ifdef __PPC__ -#include <asm/ppc4xx.h> -#endif -#include <asm/processor.h> - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static int write_word (flash_info_t *info, ulong dest, ulong data); - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - short n; - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) { - /* set sector offsets for bottom boot block type */ - for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */ - info->start[i] = base; - base += 8 << 10; - } - while (i < info->sector_count) { /* 64k regular sectors */ - info->start[i] = base; - base += 64 << 10; - ++i; - } - } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) { - /* set sector offsets for top boot block type */ - base += info->size; - i = info->sector_count; - for (n=0; n<8; ++n) { /* 8 x 8k boot sectors */ - base -= 8 << 10; - --i; - info->start[i] = base; - } - while (i > 0) { /* 64k regular sectors */ - base -= 64 << 10; - --i; - info->start[i] = base; - } - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - int k; - int size; - int erased; - volatile unsigned long *flash; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_EXCEL: printf ("Excel Semiconductor "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 M, top sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 M, bottom sector)\n"); - break; - case FLASH_AMDL322T: printf ("AM29DL322T (32 M, top sector)\n"); - break; - case FLASH_AMDL322B: printf ("AM29DL322B (32 M, bottom sector)\n"); - break; - case FLASH_AMDL323T: printf ("AM29DL323T (32 M, top sector)\n"); - break; - case FLASH_AMDL323B: printf ("AM29DL323B (32 M, bottom sector)\n"); - break; - case FLASH_AM640U: printf ("AM29LV640D (64 M, uniform sector)\n"); - break; - case FLASH_SST800A: printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n"); - break; - case FLASH_SST160A: printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n"); - break; - case FLASH_SST320: printf ("SST39LF/VF320 (32 Mbit, uniform sector size)\n"); - break; - case FLASH_SST640: printf ("SST39LF/VF640 (64 Mbit, uniform sector size)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { -#ifdef CONFIG_SYS_FLASH_EMPTY_INFO - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count-1)) - size = info->start[i+1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *)info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k=0; k<size; k++) - { - if (*flash++ != 0xffffffff) - { - erased = 0; - break; - } - } - - if ((i % 5) == 0) - printf ("\n "); - /* print empty and read-only info */ - printf (" %08lX%s%s", - info->start[i], - erased ? " E" : " ", - info->protect[i] ? "RO " : " "); -#else - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); -#endif - - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - short n; - CONFIG_SYS_FLASH_WORD_SIZE value; - ulong base = (ulong)addr; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)addr; - - /* Write auto select command: read Manufacturer ID */ - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00900090; - - value = addr2[CONFIG_SYS_FLASH_READ0]; - - switch (value) { - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE)FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE)SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE)EXCEL_MANUFACT: - info->flash_id = FLASH_MAN_EXCEL; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr2[CONFIG_SYS_FLASH_READ1]; /* device ID */ - - switch (value) { - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322T: - info->flash_id += FLASH_AMDL322T; - info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322B: - info->flash_id += FLASH_AMDL322B; - info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323T: - info->flash_id += FLASH_AMDL323T; - info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323B: - info->flash_id += FLASH_AMDL323B; - info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV640U: - info->flash_id += FLASH_AM640U; - info->sector_count = 128; - info->size = 0x00800000; break; /* => 8 MB */ - -#if !(defined(CONFIG_ADCIOP) || defined(CONFIG_DASA_SIM)) - case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF800A: - info->flash_id += FLASH_SST800A; - info->sector_count = 16; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF160A: - case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF1601: - case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF1602: - info->flash_id += FLASH_SST160A; - info->sector_count = 32; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF3201: - case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF3202: - info->flash_id += FLASH_SST320; - info->sector_count = 64; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF6401: - case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF6402: - info->flash_id += FLASH_SST640; - info->sector_count = 128; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) { - /* set sector offsets for bottom boot block type */ - for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */ - info->start[i] = base; - base += 8 << 10; - } - while (i < info->sector_count) { /* 64k regular sectors */ - info->start[i] = base; - base += 64 << 10; - ++i; - } - } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) { - /* set sector offsets for top boot block type */ - base += info->size; - i = info->sector_count; - for (n=0; n<8; ++n) { /* 8 x 8k boot sectors */ - base -= 8 << 10; - --i; - info->start[i] = base; - } - while (i > 0) { /* 64k regular sectors */ - base -= 64 << 10; - --i; - info->start[i] = base; - } - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]); - if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_AMD) - info->protect[i] = 0; - else - info->protect[i] = addr2[CONFIG_SYS_FLASH_READ2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0]; - *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; - int flag, prot, sect, l_sect; - ulong start, now, last; - int i; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[sect]); - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00500050; /* block erase */ - for (i=0; i<50; i++) - udelay(1000); /* wait 1 ms */ - } else { - if (sect == s_first) { - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; - } - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00300030; /* sector erase */ - } - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[l_sect]); - while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) != (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0]; - addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - ulong *data_ptr = &data; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest; - volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)data_ptr; - ulong start; - int flag; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - for (i=0; i<4/sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) - { - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) != - (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/esd/common/fpga.c b/board/esd/common/fpga.c deleted file mode 100644 index 5c70b47..0000000 --- a/board/esd/common/fpga.c +++ /dev/null @@ -1,261 +0,0 @@ -/* - * (C) Copyright 2001-2004 - * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <command.h> - -/* ------------------------------------------------------------------------- */ - -#ifdef FPGA_DEBUG -#define DBG(x...) printf(x) -#else -#define DBG(x...) -#endif /* DEBUG */ - -#define MAX_ONES 226 - -#ifdef CONFIG_SYS_FPGA_PRG -# define FPGA_PRG CONFIG_SYS_FPGA_PRG /* FPGA program pin (ppc output) */ -# define FPGA_CLK CONFIG_SYS_FPGA_CLK /* FPGA clk pin (ppc output) */ -# define FPGA_DATA CONFIG_SYS_FPGA_DATA /* FPGA data pin (ppc output) */ -# define FPGA_DONE CONFIG_SYS_FPGA_DONE /* FPGA done pin (ppc input) */ -# define FPGA_INIT CONFIG_SYS_FPGA_INIT /* FPGA init pin (ppc input) */ -#else -# define FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ -# define FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ -# define FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ -# define FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */ -# define FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */ -#endif - -#define ERROR_FPGA_PRG_INIT_LOW -1 /* Timeout after PRG* asserted */ -#define ERROR_FPGA_PRG_INIT_HIGH -2 /* Timeout after PRG* deasserted */ -#define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */ - -#ifndef SET_FPGA -# define SET_FPGA(data) out_be32((void *)GPIO0_OR, data) -#endif - -#ifdef FPGA_PROG_ACTIVE_HIGH -# define FPGA_PRG_LOW FPGA_PRG -# define FPGA_PRG_HIGH 0 -#else -# define FPGA_PRG_LOW 0 -# define FPGA_PRG_HIGH FPGA_PRG -#endif - -#define FPGA_CLK_LOW 0 -#define FPGA_CLK_HIGH FPGA_CLK - -#define FPGA_DATA_LOW 0 -#define FPGA_DATA_HIGH FPGA_DATA - -#define FPGA_WRITE_1 { \ - SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW | FPGA_DATA_HIGH); /* set clock to 0 */ \ - SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW | FPGA_DATA_HIGH); /* set data to 1 */ \ - SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set clock to 1 */ \ - SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);} /* set data to 1 */ - -#define FPGA_WRITE_0 { \ - SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW | FPGA_DATA_HIGH); /* set clock to 0 */ \ - SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW | FPGA_DATA_LOW); /* set data to 0 */ \ - SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_LOW); /* set clock to 1 */ \ - SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);} /* set data to 1 */ - -#ifndef FPGA_DONE_STATE -# define FPGA_DONE_STATE (in_be32((void *)GPIO0_IR) & FPGA_DONE) -#endif -#ifndef FPGA_INIT_STATE -# define FPGA_INIT_STATE (in_be32((void *)GPIO0_IR) & FPGA_INIT) -#endif - - -static int fpga_boot (const unsigned char *fpgadata, int size) -{ - int i, index, len; - int count; - unsigned char b; - -#ifdef CONFIG_SYS_FPGA_SPARTAN2 - int j; -#else - int bit; -#endif - - /* display infos on fpgaimage */ - index = 15; - for (i = 0; i < 4; i++) { - len = fpgadata[index]; - DBG ("FPGA: %s\n", &(fpgadata[index + 1])); - index += len + 3; - } - -#ifdef CONFIG_SYS_FPGA_SPARTAN2 - /* search for preamble 0xFFFFFFFF */ - while (1) { - if ((fpgadata[index] == 0xff) && (fpgadata[index + 1] == 0xff) - && (fpgadata[index + 2] == 0xff) - && (fpgadata[index + 3] == 0xff)) - break; /* preamble found */ - else - index++; - } -#else - /* search for preamble 0xFF2X */ - for (index = 0; index < size - 1; index++) { - if ((fpgadata[index] == 0xff) - && ((fpgadata[index + 1] & 0xf0) == 0x30)) - break; - } - index += 2; -#endif - - DBG ("FPGA: configdata starts at position 0x%x\n", index); - DBG ("FPGA: length of fpga-data %d\n", size - index); - - /* - * Setup port pins for fpga programming - */ -#ifndef CONFIG_M5249 - out_be32 ((void *)GPIO0_ODR, 0x00000000); /* no open drain pins */ - /* setup for output */ - out_be32 ((void *)GPIO0_TCR, - in_be32 ((void *)GPIO0_TCR) | - FPGA_PRG | FPGA_CLK | FPGA_DATA); -#endif - SET_FPGA (FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set pins to high */ - - DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE"); - DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT"); - - /* - * Init fpga by asserting and deasserting PROGRAM* - */ - SET_FPGA (FPGA_PRG_LOW | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set prog active */ - - /* Wait for FPGA init line low */ - count = 0; - while (FPGA_INIT_STATE) { - udelay (1000); /* wait 1ms */ - /* Check for timeout - 100us max, so use 3ms */ - if (count++ > 3) { - DBG ("FPGA: Booting failed!\n"); - return ERROR_FPGA_PRG_INIT_LOW; - } - } - - DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE"); - DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT"); - - /* deassert PROGRAM* */ - SET_FPGA (FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set prog inactive */ - - /* Wait for FPGA end of init period . */ - count = 0; - while (!(FPGA_INIT_STATE)) { - udelay (1000); /* wait 1ms */ - /* Check for timeout */ - if (count++ > 3) { - DBG ("FPGA: Booting failed!\n"); - return ERROR_FPGA_PRG_INIT_HIGH; - } - } - - DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE"); - DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT"); - - DBG ("write configuration data into fpga\n"); - /* write configuration-data into fpga... */ - -#ifdef CONFIG_SYS_FPGA_SPARTAN2 - /* - * Load uncompressed image into fpga - */ - for (i = index; i < size; i++) { - b = fpgadata[i]; - for (j = 0; j < 8; j++) { - if ((b & 0x80) == 0x80) { - FPGA_WRITE_1; - } else { - FPGA_WRITE_0; - } - b <<= 1; - } - } -#else - /* send 0xff 0x20 */ - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_0; - FPGA_WRITE_0; - FPGA_WRITE_1; - FPGA_WRITE_0; - FPGA_WRITE_0; - FPGA_WRITE_0; - FPGA_WRITE_0; - FPGA_WRITE_0; - - /* - ** Bit_DeCompression - ** Code 1 .. maxOnes : n '1's followed by '0' - ** maxOnes + 1 .. maxOnes + 1 : n - 1 '1's no '0' - ** maxOnes + 2 .. 254 : n - (maxOnes + 2) '0's followed by '1' - ** 255 : '1' - */ - - for (i = index; i < size; i++) { - b = fpgadata[i]; - if ((b >= 1) && (b <= MAX_ONES)) { - for (bit = 0; bit < b; bit++) { - FPGA_WRITE_1; - } - FPGA_WRITE_0; - } else if (b == (MAX_ONES + 1)) { - for (bit = 1; bit < b; bit++) { - FPGA_WRITE_1; - } - } else if ((b >= (MAX_ONES + 2)) && (b <= 254)) { - for (bit = 0; bit < (b - (MAX_ONES + 2)); bit++) { - FPGA_WRITE_0; - } - FPGA_WRITE_1; - } else if (b == 255) { - FPGA_WRITE_1; - } - } -#endif - - DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE"); - DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT"); - - /* - * Check if fpga's DONE signal - correctly booted ? - */ - - /* Wait for FPGA end of programming period . */ - count = 0; - while (!(FPGA_DONE_STATE)) { - udelay (1000); /* wait 1ms */ - /* Check for timeout */ - if (count++ > 3) { - DBG ("FPGA: Booting failed!\n"); - return ERROR_FPGA_PRG_DONE; - } - } - - DBG ("FPGA: Booting successful!\n"); - return 0; -} diff --git a/board/esd/common/lcd.c b/board/esd/common/lcd.c deleted file mode 100644 index 29421fc..0000000 --- a/board/esd/common/lcd.c +++ /dev/null @@ -1,359 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * (C) Copyright 2005 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm/io.h> -#include "lcd.h" - - -extern int video_display_bitmap (ulong, int, int); - - -int palette_index; -int palette_value; -int lcd_depth; -unsigned char *glob_lcd_reg; -unsigned char *glob_lcd_mem; - -#if defined(CONFIG_SYS_LCD_ENDIAN) -void lcd_setup(int lcd, int config) -{ - if (lcd == 0) { - /* - * Set endianess and reset lcd controller 0 (small) - */ - - /* set reset to low */ - out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_LCD0_RST); - udelay(10); /* wait 10us */ - if (config == 1) { - /* big-endian */ - out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD_ENDIAN); - } else { - /* little-endian */ - out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_LCD_ENDIAN); - } - udelay(10); /* wait 10us */ - /* set reset to high */ - out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD0_RST); - } else { - /* - * Set endianess and reset lcd controller 1 (big) - */ - - /* set reset to low */ - out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_LCD1_RST); - udelay(10); /* wait 10us */ - if (config == 1) { - /* big-endian */ - out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD_ENDIAN); - } else { - /* little-endian */ - out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_LCD_ENDIAN); - } - udelay(10); /* wait 10us */ - /* set reset to high */ - out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD1_RST); - } - - /* - * CONFIG_SYS_LCD_ENDIAN may also be FPGA_RESET, so set inactive - */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD_ENDIAN); -} -#endif /* CONFIG_SYS_LCD_ENDIAN */ - - -int lcd_bmp(uchar *logo_bmp) -{ - int i; - uchar *ptr; - ushort *ptr2; - ushort val; - unsigned char *dst = NULL; - int x, y; - int width, height, bpp, colors, line_size; - int header_size; - unsigned char *bmp; - unsigned char r, g, b; - BITMAPINFOHEADER *bm_info; - ulong len; - - /* - * Check for bmp mark 'BM' - */ - if (*(ushort *)logo_bmp != 0x424d) { - /* - * Decompress bmp image - */ - len = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE; - dst = malloc(CONFIG_SYS_VIDEO_LOGO_MAX_SIZE); - if (dst == NULL) { - printf("Error: malloc for gunzip failed!\n"); - return 1; - } - if (gunzip(dst, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE, - (uchar *)logo_bmp, &len) != 0) { - free(dst); - return 1; - } - if (len == CONFIG_SYS_VIDEO_LOGO_MAX_SIZE) { - printf("Image could be truncated" - " (increase CONFIG_SYS_VIDEO_LOGO_MAX_SIZE)!\n"); - } - - /* - * Check for bmp mark 'BM' - */ - if (*(ushort *)dst != 0x424d) { - printf("LCD: Unknown image format!\n"); - free(dst); - return 1; - } - } else { - /* - * Uncompressed BMP image, just use this pointer - */ - dst = (uchar *)logo_bmp; - } - - /* - * Get image info from bmp-header - */ - bm_info = (BITMAPINFOHEADER *)(dst + 14); - bpp = LOAD_SHORT(bm_info->biBitCount); - width = LOAD_LONG(bm_info->biWidth); - height = LOAD_LONG(bm_info->biHeight); - switch (bpp) { - case 1: - colors = 1; - line_size = width >> 3; - break; - case 4: - colors = 16; - line_size = width >> 1; - break; - case 8: - colors = 256; - line_size = width; - break; - case 24: - colors = 0; - line_size = width * 3; - break; - default: - printf("LCD: Unknown bpp (%d) im image!\n", bpp); - if ((dst != NULL) && (dst != (uchar *)logo_bmp)) - free(dst); - return 1; - } - printf(" (%d*%d, %dbpp)\n", width, height, bpp); - - /* - * Write color palette - */ - if ((colors <= 256) && (lcd_depth <= 8)) { - ptr = (unsigned char *)(dst + 14 + 40); - for (i = 0; i < colors; i++) { - b = *ptr++; - g = *ptr++; - r = *ptr++; - ptr++; - S1D_WRITE_PALETTE(glob_lcd_reg, i, r, g, b); - } - } - - /* - * Write bitmap data into framebuffer - */ - ptr = glob_lcd_mem; - ptr2 = (ushort *)glob_lcd_mem; - header_size = 14 + 40 + 4*colors; /* skip bmp header */ - for (y = 0; y < height; y++) { - bmp = &dst[(height-1-y)*line_size + header_size]; - if (lcd_depth == 16) { - if (bpp == 24) { - for (x = 0; x < width; x++) { - /* - * Generate epson 16bpp fb-format - * from 24bpp image - */ - b = *bmp++ >> 3; - g = *bmp++ >> 2; - r = *bmp++ >> 3; - val = ((r & 0x1f) << 11) | - ((g & 0x3f) << 5) | - (b & 0x1f); - *ptr2++ = val; - } - } else if (bpp == 8) { - for (x = 0; x < line_size; x++) { - /* query rgb value from palette */ - ptr = (unsigned char *)(dst + 14 + 40); - ptr += (*bmp++) << 2; - b = *ptr++ >> 3; - g = *ptr++ >> 2; - r = *ptr++ >> 3; - val = ((r & 0x1f) << 11) | - ((g & 0x3f) << 5) | - (b & 0x1f); - *ptr2++ = val; - } - } - } else { - for (x = 0; x < line_size; x++) - *ptr++ = *bmp++; - } - } - - if ((dst != NULL) && (dst != (uchar *)logo_bmp)) - free(dst); - return 0; -} - - -int lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count, - uchar *logo_bmp, ulong len) -{ - int i; - ushort s1dReg; - uchar s1dValue; - int reg_byte_swap; - - /* - * Detect epson - */ - out_8(&lcd_reg[0], 0x00); - out_8(&lcd_reg[1], 0x00); - - if (in_8(&lcd_reg[0]) == 0x1c) { - /* - * Big epson detected - */ - reg_byte_swap = false; - palette_index = 0x1e2; - palette_value = 0x1e4; - lcd_depth = 16; - puts("LCD: S1D13806"); - } else if (in_8(&lcd_reg[1]) == 0x1c) { - /* - * Big epson detected (with register swap bug) - */ - reg_byte_swap = true; - palette_index = 0x1e3; - palette_value = 0x1e5; - lcd_depth = 16; - puts("LCD: S1D13806S"); - } else if (in_8(&lcd_reg[0]) == 0x18) { - /* - * Small epson detected (704) - */ - reg_byte_swap = false; - palette_index = 0x15; - palette_value = 0x17; - lcd_depth = 8; - puts("LCD: S1D13704"); - } else if (in_8(&lcd_reg[0x10000]) == 0x24) { - /* - * Small epson detected (705) - */ - reg_byte_swap = false; - palette_index = 0x15; - palette_value = 0x17; - lcd_depth = 8; - lcd_reg += 0x10000; /* add offset for 705 regs */ - puts("LCD: S1D13705"); - } else { - out_8(&lcd_reg[0x1a], 0x00); - udelay(1000); - if (in_8(&lcd_reg[1]) == 0x0c) { - /* - * S1D13505 detected - */ - reg_byte_swap = true; - palette_index = 0x25; - palette_value = 0x27; - lcd_depth = 16; - - puts("LCD: S1D13505"); - } else { - puts("LCD: No controller detected!\n"); - return 1; - } - } - - /* - * Setup lcd controller regs - */ - for (i = 0; i < reg_count; i++) { - s1dReg = regs[i].Index; - if (reg_byte_swap) { - if ((s1dReg & 0x0001) == 0) - s1dReg |= 0x0001; - else - s1dReg &= ~0x0001; - } - s1dValue = regs[i].Value; - out_8(&lcd_reg[s1dReg], s1dValue); - } - - /* - * Save reg & mem pointer for later usage (e.g. bmp command) - */ - glob_lcd_reg = lcd_reg; - glob_lcd_mem = lcd_mem; - - /* - * Display bmp image - */ - return lcd_bmp(logo_bmp); -} - -int do_esdbmp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - ulong addr; -#ifdef CONFIG_VIDEO_SM501 - char *str; -#endif - if (argc != 2) - return cmd_usage(cmdtp); - - addr = simple_strtoul(argv[1], NULL, 16); - -#ifdef CONFIG_VIDEO_SM501 - str = getenv("bd_type"); - if ((strcmp(str, "ppc221") == 0) || (strcmp(str, "ppc231") == 0)) { - /* - * SM501 available, use standard bmp command - */ - return video_display_bitmap(addr, 0, 0); - } else { - /* - * No SM501 available, use esd epson bmp command - */ - return lcd_bmp((uchar *)addr); - } -#else - return lcd_bmp((uchar *)addr); -#endif -} - -U_BOOT_CMD( - esdbmp, 2, 1, do_esdbmp, - "display BMP image", - "<imageAddr> - display image" -); diff --git a/board/esd/common/lcd.h b/board/esd/common/lcd.h deleted file mode 100644 index 5b14bf9..0000000 --- a/board/esd/common/lcd.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Neutralize little endians. - */ -#define SWAP_LONG(data) ((unsigned long) \ - (((unsigned long)(data) >> 24) | \ - ((unsigned long)(data) << 24) | \ - (((unsigned long)(data) >> 8) & 0x0000ff00 ) | \ - (((unsigned long)(data) << 8) & 0x00ff0000 ))) -#define SWAP_SHORT(data) ((unsigned short) \ - (((unsigned short)(data) >> 8 ) | \ - ((unsigned short)(data) << 8 ))) -#define LOAD_LONG(data) SWAP_LONG(data) -#define LOAD_SHORT(data) SWAP_SHORT(data) - -#define S1D_WRITE_PALETTE(p,i,r,g,b) \ - { \ - out_8(&((uchar*)(p))[palette_index], (uchar)(i)); \ - out_8(&((uchar*)(p))[palette_index], (uchar)(r)); \ - out_8(&((uchar*)(p))[palette_index], (uchar)(g)); \ - out_8(&((uchar*)(p))[palette_index], (uchar)(b)); \ - } - -typedef struct -{ - ushort Index; - uchar Value; -} S1D_REGS; - -typedef struct /**** BMP file info structure ****/ -{ - unsigned int biSize; /* Size of info header */ - int biWidth; /* Width of image */ - int biHeight; /* Height of image */ - unsigned short biPlanes; /* Number of color planes */ - unsigned short biBitCount; /* Number of bits per pixel */ - unsigned int biCompression; /* Type of compression to use */ - unsigned int biSizeImage; /* Size of image data */ - int biXPelsPerMeter; /* X pixels per meter */ - int biYPelsPerMeter; /* Y pixels per meter */ - unsigned int biClrUsed; /* Number of colors used */ - unsigned int biClrImportant; /* Number of important colors */ -} BITMAPINFOHEADER; diff --git a/board/esd/common/misc.c b/board/esd/common/misc.c deleted file mode 100644 index 79cd612..0000000 --- a/board/esd/common/misc.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * (C) Copyright 2004 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> - -#ifdef CONFIG_LXT971_NO_SLEEP -#include <miiphy.h> -#endif - - -#ifdef CONFIG_LXT971_NO_SLEEP -void lxt971_no_sleep(void) -{ - unsigned short reg; - - miiphy_read("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, ®); - reg &= ~0x0040; /* disable sleep mode */ - miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, reg); -} -#endif /* CONFIG_LXT971_NO_SLEEP */ diff --git a/board/esd/common/pci.c b/board/esd/common/pci.c deleted file mode 100644 index faebdb1..0000000 --- a/board/esd/common/pci.c +++ /dev/null @@ -1,186 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> -#include <pci.h> - - -u_long pci9054_iobase; - - -#define PCI_PRIMARY_CAR (0x500000dc) /* PCI config address reg */ -#define PCI_PRIMARY_CDR (0x80000000) /* PCI config data reg */ - - -/*-----------------------------------------------------------------------------+ -| Subroutine: pci9054_read_config_dword -| Description: Read a PCI configuration register -| Inputs: -| hose PCI Controller -| dev PCI Bus+Device+Function number -| offset Configuration register number -| value Address of the configuration register value -| Return value: -| 0 Successful -+-----------------------------------------------------------------------------*/ -int pci9054_read_config_dword(struct pci_controller *hose, - pci_dev_t dev, int offset, u32* value) -{ - unsigned long conAdrVal; - unsigned long val; - - /* generate coded value for CON_ADR register */ - conAdrVal = dev | (offset & 0xfc) | 0x80000000; - - /* Load the CON_ADR (CAR) value first, then read from CON_DATA (CDR) */ - *(unsigned long *)PCI_PRIMARY_CAR = conAdrVal; - - /* Note: *pResult comes back as -1 if machine check happened */ - val = in32r(PCI_PRIMARY_CDR); - - *value = (unsigned long) val; - - out32r(PCI_PRIMARY_CAR, 0); - - if ((*(unsigned long *)0x50000304) & 0x60000000) - { - /* clear pci master/target abort bits */ - *(unsigned long *)0x50000304 = *(unsigned long *)0x50000304; - } - - return 0; -} - -/*-----------------------------------------------------------------------------+ -| Subroutine: pci9054_write_config_dword -| Description: Write a PCI configuration register. -| Inputs: -| hose PCI Controller -| dev PCI Bus+Device+Function number -| offset Configuration register number -| Value Configuration register value -| Return value: -| 0 Successful -| Updated for pass2 errata #6. Need to disable interrupts and clear the -| PCICFGADR reg after writing the PCICFGDATA reg. -+-----------------------------------------------------------------------------*/ -int pci9054_write_config_dword(struct pci_controller *hose, - pci_dev_t dev, int offset, u32 value) -{ - unsigned long conAdrVal; - - conAdrVal = dev | (offset & 0xfc) | 0x80000000; - - *(unsigned long *)PCI_PRIMARY_CAR = conAdrVal; - - out32r(PCI_PRIMARY_CDR, value); - - out32r(PCI_PRIMARY_CAR, 0); - - /* clear pci master/target abort bits */ - *(unsigned long *)0x50000304 = *(unsigned long *)0x50000304; - - return (0); -} - -/*----------------------------------------------------------------------- - */ - -#ifdef CONFIG_DASA_SIM -static void pci_dasa_sim_config_pci9054(struct pci_controller *hose, pci_dev_t dev, - struct pci_config_table *_) -{ - unsigned int iobase; - unsigned short status = 0; - unsigned char timer; - - /* - * Configure PLX PCI9054 - */ - pci_read_config_word(CONFIG_SYS_PCI9054_DEV_FN, PCI_COMMAND, &status); - status |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY; - pci_write_config_word(CONFIG_SYS_PCI9054_DEV_FN, PCI_COMMAND, status); - - /* Check the latency timer for values >= 0x60. - */ - pci_read_config_byte(CONFIG_SYS_PCI9054_DEV_FN, PCI_LATENCY_TIMER, &timer); - if (timer < 0x60) - { - pci_write_config_byte(CONFIG_SYS_PCI9054_DEV_FN, PCI_LATENCY_TIMER, 0x60); - } - - /* Set I/O base register. - */ - pci_write_config_dword(CONFIG_SYS_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, CONFIG_SYS_PCI9054_IOBASE); - pci_read_config_dword(CONFIG_SYS_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, &iobase); - - pci9054_iobase = pci_mem_to_phys(CONFIG_SYS_PCI9054_DEV_FN, iobase & PCI_BASE_ADDRESS_MEM_MASK); - - if (pci9054_iobase == 0xffffffff) - { - printf("Error: Can not set I/O base register.\n"); - return; - } -} -#endif - -static struct pci_config_table pci9054_config_table[] = { -#ifndef CONFIG_PCI_PNP - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_BUS(CONFIG_SYS_ETH_DEV_FN), PCI_DEV(CONFIG_SYS_ETH_DEV_FN), PCI_FUNC(CONFIG_SYS_ETH_DEV_FN), - pci_cfgfunc_config_device, { CONFIG_SYS_ETH_IOBASE, - CONFIG_SYS_ETH_IOBASE, - PCI_COMMAND_IO | PCI_COMMAND_MASTER }}, -#ifdef CONFIG_DASA_SIM - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_BUS(CONFIG_SYS_PCI9054_DEV_FN), PCI_DEV(CONFIG_SYS_PCI9054_DEV_FN), PCI_FUNC(CONFIG_SYS_PCI9054_DEV_FN), - pci_dasa_sim_config_pci9054 }, -#endif -#endif - { } -}; - -static struct pci_controller pci9054_hose = { - config_table: pci9054_config_table, -}; - -void pci_init_board(void) -{ - struct pci_controller *hose = &pci9054_hose; - - /* - * Register the hose - */ - hose->first_busno = 0; - hose->last_busno = 0xff; - - /* System memory space */ - pci_set_region(hose->regions + 0, - 0x00000000, 0x00000000, 0x01000000, - PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); - - /* PCI Memory space */ - pci_set_region(hose->regions + 1, - 0x00000000, 0xc0000000, 0x10000000, - PCI_REGION_MEM); - - pci_set_ops(hose, - pci_hose_read_config_byte_via_dword, - pci_hose_read_config_word_via_dword, - pci9054_read_config_dword, - pci_hose_write_config_byte_via_dword, - pci_hose_write_config_word_via_dword, - pci9054_write_config_dword); - - hose->region_count = 2; - - pci_register_hose(hose); - - hose->last_busno = pci_hose_scan(hose); -} diff --git a/board/esd/common/s1d13505_640_480_16bpp.h b/board/esd/common/s1d13505_640_480_16bpp.h deleted file mode 100644 index ca11683..0000000 --- a/board/esd/common/s1d13505_640_480_16bpp.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * (C) Copyright 2008 - * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Panel: 640x480 50Hz TFT Single 18-bit (PCLK=20.000 MHz) - * Memory: DRAM (MCLK=40.000 MHz) - */ -static S1D_REGS regs_13505_640_480_16bpp[] = -{ - {0x1B,0x00}, /* Miscellaneous Register */ - {0x23,0x20}, /* Performance Enhancement Register 1 */ - {0x01,0x30}, /* Memory Configuration Register */ - {0x22,0x24}, /* Performance Enhancement Register 0 */ - {0x02,0x25}, /* Panel Type Register */ - {0x03,0x00}, /* MOD Rate Register */ - {0x04,0x4F}, /* Horizontal Display Width Register */ - {0x05,0x0c}, /* Horizontal Non-Display Period Register */ - {0x06,0x00}, /* HRTC/FPLINE Start Position Register */ - {0x07,0x01}, /* HRTC/FPLINE Pulse Width Register */ - {0x08,0xDF}, /* Vertical Display Height Register 0 */ - {0x09,0x01}, /* Vertical Display Height Register 1 */ - {0x0A,0x3E}, /* Vertical Non-Display Period Register */ - {0x0B,0x00}, /* VRTC/FPFRAME Start Position Register */ - {0x0C,0x01}, /* VRTC/FPFRAME Pulse Width Register */ - {0x0E,0xFF}, /* Screen 1 Line Compare Register 0 */ - {0x0F,0x03}, /* Screen 1 Line Compare Register 1 */ - {0x10,0x00}, /* Screen 1 Display Start Address Register 0 */ - {0x11,0x00}, /* Screen 1 Display Start Address Register 1 */ - {0x12,0x00}, /* Screen 1 Display Start Address Register 2 */ - {0x13,0x00}, /* Screen 2 Display Start Address Register 0 */ - {0x14,0x00}, /* Screen 2 Display Start Address Register 1 */ - {0x15,0x00}, /* Screen 2 Display Start Address Register 2 */ - {0x16,0x80}, /* Memory Address Offset Register 0 */ - {0x17,0x02}, /* Memory Address Offset Register 1 */ - {0x18,0x00}, /* Pixel Panning Register */ - {0x19,0x01}, /* Clock Configuration Register */ - {0x1A,0x00}, /* Power Save Configuration Register */ - {0x1C,0x00}, /* MD Configuration Readback Register 0 */ - {0x1E,0x06}, /* General IO Pins Configuration Register 0 */ - {0x1F,0x00}, /* General IO Pins Configuration Register 1 */ - {0x20,0x00}, /* General IO Pins Control Register 0 */ - {0x21,0x00}, /* General IO Pins Control Register 1 */ - {0x23,0x20}, /* Performance Enhancement Register 1 */ - {0x0D,0x15}, /* Display Mode Register */ -}; diff --git a/board/esd/common/s1d13704_320_240_4bpp.h b/board/esd/common/s1d13704_320_240_4bpp.h deleted file mode 100644 index bd910e8..0000000 --- a/board/esd/common/s1d13704_320_240_4bpp.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2000,2001 Epson Research and Development, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Generic Header information generated by 13704CFG.EXE (Build 10) - * Panel: 320x240x4bpp 78Hz Mono 4-Bit STN, Disabled (PCLK=6.666MHz) - */ - -static S1D_REGS regs_13704_320_240_4bpp[] = -{ - { 0x00, 0x00 }, /* Revision Code Register */ - { 0x01, 0x04 }, /*00*/ /* Mode Register 0 Register */ - { 0x02, 0xA4 }, /*a0*/ /* Mode Register 1 Register */ - { 0x03, 0x83 }, /*03*/ /* Mode Register 2 Register - bit7 is LUT bypass */ - { 0x04, 0x27 }, /* Horizontal Panel Size Register */ - { 0x05, 0xEF }, /* Vertical Panel Size Register (LSB) */ - { 0x06, 0x00 }, /* Vertical Panel Size Register (MSB) */ - { 0x07, 0x00 }, /* FPLINE Start Position Register */ - { 0x08, 0x00 }, /* Horizontal Non-Display Period Register */ - { 0x09, 0x00 }, /* FPFRAME Start Position Register */ - { 0x0A, 0x02 }, /* Vertical Non-Display Period Register */ - { 0x0B, 0x00 }, /* MOD Rate Register */ - { 0x0C, 0x00 }, /* Screen 1 Start Address Register (LSB) */ - { 0x0D, 0x00 }, /* Screen 1 Start Address Register (MSB) */ - { 0x0E, 0x00 }, /* Not Used */ - { 0x0F, 0x00 }, /* Screen 2 Start Address Register (LSB) */ - { 0x10, 0x00 }, /* Screen 2 Start Address Register (MSB) */ - { 0x11, 0x00 }, /* Not Used */ - { 0x12, 0x00 }, /* Memory Address Offset Register */ - { 0x13, 0xFF }, /* Screen 1 Vertical Size Register (LSB) */ - { 0x14, 0x03 }, /* Screen 1 Vertical Size Register (MSB) */ - { 0x15, 0x00 }, /* Look-Up Table Address Register */ - { 0x16, 0x00 }, /* Look-Up Table Bank Select Register */ - { 0x17, 0x00 }, /* Look-Up Table Data Register */ - { 0x18, 0x01 }, /* GPIO Configuration Control Register */ - { 0x19, 0x01 }, /* GPIO Status/Control Register */ - { 0x1A, 0x00 }, /* Scratch Pad Register */ - { 0x1B, 0x00 }, /* SwivelView Mode Register */ - { 0x1C, 0xA0 }, /* Line Byte Count Register */ - { 0x1D, 0x00 }, /* Not Used */ - { 0x1E, 0x00 }, /* Not Used */ - { 0x1F, 0x00 }, /* Not Used */ -}; diff --git a/board/esd/common/s1d13705_320_240_8bpp.h b/board/esd/common/s1d13705_320_240_8bpp.h deleted file mode 100644 index 041b4a9..0000000 --- a/board/esd/common/s1d13705_320_240_8bpp.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2000,2001 Epson Research and Development, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Generic Header information generated by 13704CFG.EXE (Build 10) - * Panel: 320x240x8bpp 78Hz Mono 8-Bit STN, Disabled (PCLK=6.666MHz) - */ - -static S1D_REGS regs_13705_320_240_8bpp[] = -{ - { 0x00, 0x00 }, /* Revision Code Register */ - { 0x01, 0x23 }, /* Mode Register 0 Register */ - { 0x02, 0xE0 }, /* Mode Register 1 Register */ - { 0x03, 0x03 }, /* Mode Register 2 Register - bit7 is LUT bypass */ - { 0x04, 0x27 }, /* Horizontal Panel Size Register */ - { 0x05, 0xEF }, /* Vertical Panel Size Register (LSB) */ - { 0x06, 0x00 }, /* Vertical Panel Size Register (MSB) */ - { 0x07, 0x00 }, /* FPLINE Start Position Register */ - { 0x08, 0x00 }, /* Horizontal Non-Display Period Register */ - { 0x09, 0x01 }, /* FPFRAME Start Position Register */ - { 0x0A, 0x02 }, /* Vertical Non-Display Period Register */ - { 0x0B, 0x00 }, /* MOD Rate Register */ - { 0x0C, 0x00 }, /* Screen 1 Start Address Register (LSB) */ - { 0x0D, 0x00 }, /* Screen 1 Start Address Register (MSB) */ - { 0x0E, 0x00 }, /* Not Used */ - { 0x0F, 0x00 }, /* Screen 2 Start Address Register (LSB) */ - { 0x10, 0x00 }, /* Screen 2 Start Address Register (MSB) */ - { 0x11, 0x00 }, /* Not Used */ - { 0x12, 0x00 }, /* Memory Address Offset Register */ - { 0x13, 0xFF }, /* Screen 1 Vertical Size Register (LSB) */ - { 0x14, 0x03 }, /* Screen 1 Vertical Size Register (MSB) */ - { 0x15, 0x00 }, /* Look-Up Table Address Register */ - { 0x16, 0x00 }, /* Look-Up Table Bank Select Register */ - { 0x17, 0x00 }, /* Look-Up Table Data Register */ - { 0x18, 0x01 }, /* GPIO Configuration Control Register */ - { 0x19, 0x01 }, /* GPIO Status/Control Register */ - { 0x1A, 0x00 }, /* Scratch Pad Register */ - { 0x1B, 0x00 }, /* SwivelView Mode Register */ - { 0x1C, 0xFF }, /* Line Byte Count Register */ - { 0x1D, 0x00 }, /* Not Used */ - { 0x1E, 0x00 }, /* Not Used */ - { 0x1F, 0x00 }, /* Not Used */ -}; diff --git a/board/esd/common/s1d13806_1024_768_8bpp.h b/board/esd/common/s1d13806_1024_768_8bpp.h deleted file mode 100644 index 615fa33..0000000 --- a/board/esd/common/s1d13806_1024_768_8bpp.h +++ /dev/null @@ -1,120 +0,0 @@ -/* - * Copyright (c) 2000,2001 Epson Research and Development, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * File generated by S1D13806CFG.EXE - * Panel: (active) 1024x768 34Hz TFT Single 12-bit (PCLK=BUSCLK=33.333MHz) - * Memory: Embedded SDRAM (MCLK=CLKI=49.100MHz) (BUSCLK=33.333MHz) - */ - -static S1D_REGS regs_13806_1024_768_8bpp[] = -{ - {0x0001,0x00}, /* Miscellaneous Register */ - {0x01FC,0x00}, /* Display Mode Register */ - {0x0004,0x00}, /* General IO Pins Configuration Register 0 */ - {0x0005,0x00}, /* General IO Pins Configuration Register 1 */ - {0x0008,0x00}, /* General IO Pins Control Register 0 */ - {0x0009,0x00}, /* General IO Pins Control Register 1 */ - {0x0010,0x00}, /* Memory Clock Configuration Register */ - {0x0014,0x01}, /* LCD Pixel Clock Configuration Register */ - {0x0018,0x00}, /* CRT/TV Pixel Clock Configuration Register */ - {0x001C,0x02}, /* MediaPlug Clock Configuration Register */ - {0x001E,0x01}, /* CPU To Memory Wait State Select Register */ - {0x0021,0x03}, /* DRAM Refresh Rate Register */ - {0x002A,0x00}, /* DRAM Timings Control Register 0 */ - {0x002B,0x01}, /* DRAM Timings Control Register 1 */ - {0x0020,0x80}, /* Memory Configuration Register */ - {0x0030,0x55}, /* Panel Type Register */ - {0x0031,0x00}, /* MOD Rate Register */ - {0x0032,0x7F}, /* LCD Horizontal Display Width Register */ - {0x0034,0x12}, /* LCD Horizontal Non-Display Period Register */ - {0x0035,0x01}, /* TFT FPLINE Start Position Register */ - {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */ - {0x0038,0xFF}, /* LCD Vertical Display Height Register 0 */ - {0x0039,0x02}, /* LCD Vertical Display Height Register 1 */ - {0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */ - {0x003B,0x0A}, /* TFT FPFRAME Start Position Register */ - {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */ - {0x0040,0x03}, /* LCD Display Mode Register */ - {0x0041,0x00}, /* LCD Miscellaneous Register */ - {0x0042,0x00}, /* LCD Display Start Address Register 0 */ - {0x0043,0x00}, /* LCD Display Start Address Register 1 */ - {0x0044,0x00}, /* LCD Display Start Address Register 2 */ - {0x0046,0x00}, /* LCD Memory Address Offset Register 0 */ - {0x0047,0x02}, /* LCD Memory Address Offset Register 1 */ - {0x0048,0x00}, /* LCD Pixel Panning Register */ - {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */ - {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */ - {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */ - {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */ - {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */ - {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */ - {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */ - {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */ - {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */ - {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */ - {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */ - {0x005B,0x10}, /* TV Output Control Register */ - {0x0060,0x03}, /* CRT/TV Display Mode Register */ - {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */ - {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */ - {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */ - {0x0066,0x40}, /* CRT/TV Memory Address Offset Register 0 */ - {0x0067,0x01}, /* CRT/TV Memory Address Offset Register 1 */ - {0x0068,0x00}, /* CRT/TV Pixel Panning Register */ - {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */ - {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */ - {0x0070,0x00}, /* LCD Ink/Cursor Control Register */ - {0x0071,0x01}, /* LCD Ink/Cursor Start Address Register */ - {0x0072,0x00}, /* LCD Cursor X Position Register 0 */ - {0x0073,0x00}, /* LCD Cursor X Position Register 1 */ - {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */ - {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */ - {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */ - {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */ - {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */ - {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */ - {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */ - {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */ - {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */ - {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */ - {0x0081,0x01}, /* CRT/TV Ink/Cursor Start Address Register */ - {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */ - {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */ - {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */ - {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */ - {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */ - {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */ - {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */ - {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */ - {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */ - {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */ - {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */ - {0x0100,0x00}, /* BitBlt Control Register 0 */ - {0x0101,0x00}, /* BitBlt Control Register 1 */ - {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */ - {0x0103,0x00}, /* BitBlt Operation Register */ - {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */ - {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */ - {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */ - {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */ - {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */ - {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */ - {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */ - {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */ - {0x0110,0x00}, /* BitBlt Width Register 0 */ - {0x0111,0x00}, /* BitBlt Width Register 1 */ - {0x0112,0x00}, /* BitBlt Height Register 0 */ - {0x0113,0x00}, /* BitBlt Height Register 1 */ - {0x0114,0x00}, /* BitBlt Background Color Register 0 */ - {0x0115,0x00}, /* BitBlt Background Color Register 1 */ - {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */ - {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */ - {0x01E0,0x00}, /* Look-Up Table Mode Register */ - {0x01E2,0x00}, /* Look-Up Table Address Register */ - {0x01F0,0x10}, /* Power Save Configuration Register */ - {0x01F1,0x00}, /* Power Save Status Register */ - {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */ - {0x01FC,0x01}, /* Display Mode Register */ -}; diff --git a/board/esd/common/s1d13806_320_240_4bpp.h b/board/esd/common/s1d13806_320_240_4bpp.h deleted file mode 100644 index 2531f47..0000000 --- a/board/esd/common/s1d13806_320_240_4bpp.h +++ /dev/null @@ -1,120 +0,0 @@ -/* - * Copyright (c) 2000,2001 Epson Research and Development, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * File generated by S1D13806CFG.EXE - * Panel: (active) 320x240 62Hz STN Single 4-bit (PCLK=CLKI2/4=6.250MHz) - * Memory: Embedded SDRAM (MCLK=CLKI=49.500MHz) (BUSCLK=33.333MHz) - */ - -static S1D_REGS regs_13806_320_240_4bpp[] = -{ - {0x0001,0x00}, /* Miscellaneous Register */ - {0x01FC,0x00}, /* Display Mode Register */ - {0x0004,0x08}, /* General IO Pins Configuration Register 0 */ - {0x0005,0x08}, /* General IO Pins Configuration Register 1 */ - {0x0008,0x08}, /* General IO Pins Control Register 0 */ - {0x0009,0x00}, /* General IO Pins Control Register 1 */ - {0x0010,0x00}, /* Memory Clock Configuration Register */ - {0x0014,0x32}, /* LCD Pixel Clock Configuration Register */ - {0x0018,0x00}, /* CRT/TV Pixel Clock Configuration Register */ - {0x001C,0x02}, /* MediaPlug Clock Configuration Register */ - {0x001E,0x01}, /* CPU To Memory Wait State Select Register */ - {0x0021,0x03}, /* DRAM Refresh Rate Register */ - {0x002A,0x00}, /* DRAM Timings Control Register 0 */ - {0x002B,0x01}, /* DRAM Timings Control Register 1 */ - {0x0020,0x80}, /* Memory Configuration Register */ - {0x0030,0x00}, /* Panel Type Register */ - {0x0031,0x00}, /* MOD Rate Register */ - {0x0032,0x27}, /* LCD Horizontal Display Width Register */ - {0x0034,0x03}, /* LCD Horizontal Non-Display Period Register */ - {0x0035,0x01}, /* TFT FPLINE Start Position Register */ - {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */ - {0x0038,0xEF}, /* LCD Vertical Display Height Register 0 */ - {0x0039,0x00}, /* LCD Vertical Display Height Register 1 */ - {0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */ - {0x003B,0x0A}, /* TFT FPFRAME Start Position Register */ - {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */ - {0x0040,0x02}, /* LCD Display Mode Register */ - {0x0041,0x00}, /* LCD Miscellaneous Register */ - {0x0042,0x00}, /* LCD Display Start Address Register 0 */ - {0x0043,0x00}, /* LCD Display Start Address Register 1 */ - {0x0044,0x00}, /* LCD Display Start Address Register 2 */ - {0x0046,0x50}, /* LCD Memory Address Offset Register 0 */ - {0x0047,0x00}, /* LCD Memory Address Offset Register 1 */ - {0x0048,0x00}, /* LCD Pixel Panning Register */ - {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */ - {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */ - {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */ - {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */ - {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */ - {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */ - {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */ - {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */ - {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */ - {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */ - {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */ - {0x005B,0x10}, /* TV Output Control Register */ - {0x0060,0x03}, /* CRT/TV Display Mode Register */ - {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */ - {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */ - {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */ - {0x0066,0x40}, /* CRT/TV Memory Address Offset Register 0 */ - {0x0067,0x01}, /* CRT/TV Memory Address Offset Register 1 */ - {0x0068,0x00}, /* CRT/TV Pixel Panning Register */ - {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */ - {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */ - {0x0070,0x00}, /* LCD Ink/Cursor Control Register */ - {0x0071,0x01}, /* LCD Ink/Cursor Start Address Register */ - {0x0072,0x00}, /* LCD Cursor X Position Register 0 */ - {0x0073,0x00}, /* LCD Cursor X Position Register 1 */ - {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */ - {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */ - {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */ - {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */ - {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */ - {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */ - {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */ - {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */ - {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */ - {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */ - {0x0081,0x01}, /* CRT/TV Ink/Cursor Start Address Register */ - {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */ - {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */ - {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */ - {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */ - {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */ - {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */ - {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */ - {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */ - {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */ - {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */ - {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */ - {0x0100,0x00}, /* BitBlt Control Register 0 */ - {0x0101,0x00}, /* BitBlt Control Register 1 */ - {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */ - {0x0103,0x00}, /* BitBlt Operation Register */ - {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */ - {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */ - {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */ - {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */ - {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */ - {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */ - {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */ - {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */ - {0x0110,0x00}, /* BitBlt Width Register 0 */ - {0x0111,0x00}, /* BitBlt Width Register 1 */ - {0x0112,0x00}, /* BitBlt Height Register 0 */ - {0x0113,0x00}, /* BitBlt Height Register 1 */ - {0x0114,0x00}, /* BitBlt Background Color Register 0 */ - {0x0115,0x00}, /* BitBlt Background Color Register 1 */ - {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */ - {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */ - {0x01E0,0x00}, /* Look-Up Table Mode Register */ - {0x01E2,0x00}, /* Look-Up Table Address Register */ - {0x01F0,0x10}, /* Power Save Configuration Register */ - {0x01F1,0x00}, /* Power Save Status Register */ - {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */ - {0x01FC,0x01}, /* Display Mode Register */ -}; diff --git a/board/esd/common/s1d13806_640_480_16bpp.h b/board/esd/common/s1d13806_640_480_16bpp.h deleted file mode 100644 index 38fc1a7..0000000 --- a/board/esd/common/s1d13806_640_480_16bpp.h +++ /dev/null @@ -1,120 +0,0 @@ -/* - * Copyright (c) 2000,2001 Epson Research and Development, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * File generated by S1D13806CFG.EXE - * Panel: (active) 640x480 59Hz TFT Single 18-bit (PCLK=CLKI2=25.000MHz) - * Memory: Embedded SDRAM (MCLK=CLKI=49.152MHz) (BUSCLK=33.333MHz) - */ - -static S1D_REGS regs_13806_640_480_16bpp[] = -{ - {0x0001,0x00}, /* Miscellaneous Register */ - {0x01FC,0x00}, /* Display Mode Register */ - {0x0004,0x18}, /* General IO Pins Configuration Register 0 */ - {0x0005,0x00}, /* General IO Pins Configuration Register 1 */ - {0x0008,0x18}, /* General IO Pins Control Register 0 */ - {0x0009,0x00}, /* General IO Pins Control Register 1 */ - {0x0010,0x00}, /* Memory Clock Configuration Register */ - {0x0014,0x02}, /* LCD Pixel Clock Configuration Register */ - {0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */ - {0x001C,0x02}, /* MediaPlug Clock Configuration Register */ - {0x001E,0x01}, /* CPU To Memory Wait State Select Register */ - {0x0021,0x03}, /* DRAM Refresh Rate Register */ - {0x002A,0x00}, /* DRAM Timings Control Register 0 */ - {0x002B,0x01}, /* DRAM Timings Control Register 1 */ - {0x0020,0x80}, /* Memory Configuration Register */ - {0x0030,0x25}, /* Panel Type Register */ - {0x0031,0x00}, /* MOD Rate Register */ - {0x0032,0x4F}, /* LCD Horizontal Display Width Register */ - {0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */ - {0x0035,0x00}, /* TFT FPLINE Start Position Register */ - {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */ - {0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */ - {0x0039,0x01}, /* LCD Vertical Display Height Register 1 */ - {0x003A,0x24}, /* LCD Vertical Non-Display Period Register */ - {0x003B,0x00}, /* TFT FPFRAME Start Position Register */ - {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */ - {0x0040,0x05}, /* LCD Display Mode Register */ - {0x0041,0x00}, /* LCD Miscellaneous Register */ - {0x0042,0x00}, /* LCD Display Start Address Register 0 */ - {0x0043,0x00}, /* LCD Display Start Address Register 1 */ - {0x0044,0x00}, /* LCD Display Start Address Register 2 */ - {0x0046,0x80}, /* LCD Memory Address Offset Register 0 */ - {0x0047,0x02}, /* LCD Memory Address Offset Register 1 */ - {0x0048,0x00}, /* LCD Pixel Panning Register */ - {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */ - {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */ - {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */ - {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */ - {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */ - {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */ - {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */ - {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */ - {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */ - {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */ - {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */ - {0x005B,0x10}, /* TV Output Control Register */ - {0x0060,0x05}, /* CRT/TV Display Mode Register */ - {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */ - {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */ - {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */ - {0x0066,0x80}, /* CRT/TV Memory Address Offset Register 0 */ - {0x0067,0x02}, /* CRT/TV Memory Address Offset Register 1 */ - {0x0068,0x00}, /* CRT/TV Pixel Panning Register */ - {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */ - {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */ - {0x0070,0x00}, /* LCD Ink/Cursor Control Register */ - {0x0071,0x01}, /* LCD Ink/Cursor Start Address Register */ - {0x0072,0x00}, /* LCD Cursor X Position Register 0 */ - {0x0073,0x00}, /* LCD Cursor X Position Register 1 */ - {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */ - {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */ - {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */ - {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */ - {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */ - {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */ - {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */ - {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */ - {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */ - {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */ - {0x0081,0x01}, /* CRT/TV Ink/Cursor Start Address Register */ - {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */ - {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */ - {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */ - {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */ - {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */ - {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */ - {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */ - {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */ - {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */ - {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */ - {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */ - {0x0100,0x00}, /* BitBlt Control Register 0 */ - {0x0101,0x00}, /* BitBlt Control Register 1 */ - {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */ - {0x0103,0x00}, /* BitBlt Operation Register */ - {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */ - {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */ - {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */ - {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */ - {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */ - {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */ - {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */ - {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */ - {0x0110,0x00}, /* BitBlt Width Register 0 */ - {0x0111,0x00}, /* BitBlt Width Register 1 */ - {0x0112,0x00}, /* BitBlt Height Register 0 */ - {0x0113,0x00}, /* BitBlt Height Register 1 */ - {0x0114,0x00}, /* BitBlt Background Color Register 0 */ - {0x0115,0x00}, /* BitBlt Background Color Register 1 */ - {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */ - {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */ - {0x01E0,0x00}, /* Look-Up Table Mode Register */ - {0x01E2,0x00}, /* Look-Up Table Address Register */ - {0x01F0,0x10}, /* Power Save Configuration Register */ - {0x01F1,0x00}, /* Power Save Status Register */ - {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */ - {0x01FC,0x01}, /* Display Mode Register */ -}; diff --git a/board/esd/common/xilinx_jtag/lenval.c b/board/esd/common/xilinx_jtag/lenval.c deleted file mode 100644 index 5405efb..0000000 --- a/board/esd/common/xilinx_jtag/lenval.c +++ /dev/null @@ -1,201 +0,0 @@ -/* - * (C) Copyright 2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/*******************************************************/ -/* file: lenval.c */ -/* abstract: This file contains routines for using */ -/* the lenVal data structure. */ -/*******************************************************/ - -#include <common.h> -#include <asm/processor.h> - -#include "lenval.h" -#include "ports.h" - - -/***************************************************************************** - * Function: value - * Description: Extract the long value from the lenval array. - * Parameters: plvValue - ptr to lenval. - * Returns: long - the extracted value. - *****************************************************************************/ -long value( lenVal* plvValue ) -{ - long lValue; /* result to hold the accumulated result */ - short sIndex; - - lValue = 0; - for ( sIndex = 0; sIndex < plvValue->len ; ++sIndex ) - { - lValue <<= 8; /* shift the accumulated result */ - lValue |= plvValue->val[ sIndex]; /* get the last byte first */ - } - - return( lValue ); -} - -/***************************************************************************** - * Function: initLenVal - * Description: Initialize the lenval array with the given value. - * Assumes lValue is less than 256. - * Parameters: plv - ptr to lenval. - * lValue - the value to set. - * Returns: void. - *****************************************************************************/ -void initLenVal( lenVal* plv, - long lValue ) -{ - plv->len = 1; - plv->val[0] = (unsigned char)lValue; -} - -/***************************************************************************** - * Function: EqualLenVal - * Description: Compare two lenval arrays with an optional mask. - * Parameters: plvTdoExpected - ptr to lenval #1. - * plvTdoCaptured - ptr to lenval #2. - * plvTdoMask - optional ptr to mask (=0 if no mask). - * Returns: short - 0 = mismatch; 1 = equal. - *****************************************************************************/ -short EqualLenVal( lenVal* plvTdoExpected, - lenVal* plvTdoCaptured, - lenVal* plvTdoMask ) -{ - short sEqual; - short sIndex; - unsigned char ucByteVal1; - unsigned char ucByteVal2; - unsigned char ucByteMask; - - sEqual = 1; - sIndex = plvTdoExpected->len; - - while ( sEqual && sIndex-- ) - { - ucByteVal1 = plvTdoExpected->val[ sIndex ]; - ucByteVal2 = plvTdoCaptured->val[ sIndex ]; - if ( plvTdoMask ) - { - ucByteMask = plvTdoMask->val[ sIndex ]; - ucByteVal1 &= ucByteMask; - ucByteVal2 &= ucByteMask; - } - if ( ucByteVal1 != ucByteVal2 ) - { - sEqual = 0; - } - } - - return( sEqual ); -} - - -/***************************************************************************** - * Function: RetBit - * Description: return the (byte, bit) of lv (reading from left to right). - * Parameters: plv - ptr to lenval. - * iByte - the byte to get the bit from. - * iBit - the bit number (0=msb) - * Returns: short - the bit value. - *****************************************************************************/ -short RetBit( lenVal* plv, - int iByte, - int iBit ) -{ - /* assert( ( iByte >= 0 ) && ( iByte < plv->len ) ); */ - /* assert( ( iBit >= 0 ) && ( iBit < 8 ) ); */ - return( (short)( ( plv->val[ iByte ] >> ( 7 - iBit ) ) & 0x1 ) ); -} - -/***************************************************************************** - * Function: SetBit - * Description: set the (byte, bit) of lv equal to val - * Example: SetBit("00000000",byte, 1) equals "01000000". - * Parameters: plv - ptr to lenval. - * iByte - the byte to get the bit from. - * iBit - the bit number (0=msb). - * sVal - the bit value to set. - * Returns: void. - *****************************************************************************/ -void SetBit( lenVal* plv, - int iByte, - int iBit, - short sVal ) -{ - unsigned char ucByteVal; - unsigned char ucBitMask; - - ucBitMask = (unsigned char)(1 << ( 7 - iBit )); - ucByteVal = (unsigned char)(plv->val[ iByte ] & (~ucBitMask)); - - if ( sVal ) - { - ucByteVal |= ucBitMask; - } - plv->val[ iByte ] = ucByteVal; -} - -/***************************************************************************** - * Function: AddVal - * Description: add val1 to val2 and store in resVal; - * assumes val1 and val2 are of equal length. - * Parameters: plvResVal - ptr to result. - * plvVal1 - ptr of addendum. - * plvVal2 - ptr of addendum. - * Returns: void. - *****************************************************************************/ -void addVal( lenVal* plvResVal, - lenVal* plvVal1, - lenVal* plvVal2 ) -{ - unsigned char ucCarry; - unsigned short usSum; - unsigned short usVal1; - unsigned short usVal2; - short sIndex; - - plvResVal->len = plvVal1->len; /* set up length of result */ - - /* start at least significant bit and add bytes */ - ucCarry = 0; - sIndex = plvVal1->len; - while ( sIndex-- ) - { - usVal1 = plvVal1->val[ sIndex ]; /* i'th byte of val1 */ - usVal2 = plvVal2->val[ sIndex ]; /* i'th byte of val2 */ - - /* add the two bytes plus carry from previous addition */ - usSum = (unsigned short)( usVal1 + usVal2 + ucCarry ); - - /* set up carry for next byte */ - ucCarry = (unsigned char)( ( usSum > 255 ) ? 1 : 0 ); - - /* set the i'th byte of the result */ - plvResVal->val[ sIndex ] = (unsigned char)usSum; - } -} - -/***************************************************************************** - * Function: readVal - * Description: read from XSVF numBytes bytes of data into x. - * Parameters: plv - ptr to lenval in which to put the bytes read. - * sNumBytes - the number of bytes to read. - * Returns: void. - *****************************************************************************/ -void readVal( lenVal* plv, - short sNumBytes ) -{ - unsigned char* pucVal; - - plv->len = sNumBytes; /* set the length of the lenVal */ - for ( pucVal = plv->val; sNumBytes; --sNumBytes, ++pucVal ) - { - /* read a byte of data into the lenVal */ - readByte( pucVal ); - } -} diff --git a/board/esd/common/xilinx_jtag/lenval.h b/board/esd/common/xilinx_jtag/lenval.h deleted file mode 100644 index 3273eec..0000000 --- a/board/esd/common/xilinx_jtag/lenval.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * (C) Copyright 2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/*******************************************************/ -/* file: lenval.h */ -/* abstract: This file contains a description of the */ -/* data structure "lenval". */ -/*******************************************************/ - -#ifndef lenval_dot_h -#define lenval_dot_h - -/* the lenVal structure is a byte oriented type used to store an */ -/* arbitrary length binary value. As an example, the hex value */ -/* 0x0e3d is represented as a lenVal with len=2 (since 2 bytes */ -/* and val[0]=0e and val[1]=3d. val[2-MAX_LEN] are undefined */ - -/* maximum length (in bytes) of value to read in */ -/* this needs to be at least 4, and longer than the */ -/* length of the longest SDR instruction. If there is, */ -/* only 1 device in the chain, MAX_LEN must be at least */ -/* ceil(27/8) == 4. For 6 devices in a chain, MAX_LEN */ -/* must be 5, for 14 devices MAX_LEN must be 6, for 20 */ -/* devices MAX_LEN must be 7, etc.. */ -/* You can safely set MAX_LEN to a smaller number if you*/ -/* know how many devices will be in your chain. */ -#define MAX_LEN 7000 - - -typedef struct var_len_byte -{ - short len; /* number of chars in this value */ - unsigned char val[MAX_LEN+1]; /* bytes of data */ -} lenVal; - - -/* return the long representation of a lenVal */ -extern long value(lenVal *x); - -/* set lenVal equal to value */ -extern void initLenVal(lenVal *x, long value); - -/* check if expected equals actual (taking the mask into account) */ -extern short EqualLenVal(lenVal *expected, lenVal *actual, lenVal *mask); - -/* add val1+val2 and put the result in resVal */ -extern void addVal(lenVal *resVal, lenVal *val1, lenVal *val2); - -/* return the (byte, bit) of lv (reading from left to right) */ -extern short RetBit(lenVal *lv, int byte, int bit); - -/* set the (byte, bit) of lv equal to val (e.g. SetBit("00000000",byte, 1) - equals "01000000" */ -extern void SetBit(lenVal *lv, int byte, int bit, short val); - -/* read from XSVF numBytes bytes of data into x */ -extern void readVal(lenVal *x, short numBytes); - -#endif diff --git a/board/esd/common/xilinx_jtag/micro.c b/board/esd/common/xilinx_jtag/micro.c deleted file mode 100644 index 556636c..0000000 --- a/board/esd/common/xilinx_jtag/micro.c +++ /dev/null @@ -1,1854 +0,0 @@ -/* - * (C) Copyright 2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/***************************************************************************** - * file: micro.c - * abstract: This file contains the function, xsvfExecute(), - * call for interpreting the XSVF commands. - * Usage: Call xsvfExecute() to process XSVF data. - * The XSVF data is retrieved by readByte() in ports.c - * Remove the main function if you already have one. - * Options: XSVF_SUPPORT_COMPRESSION - * This define supports the XC9500/XL compression scheme. - * This define adds support for XSDRINC and XSETSDRMASKS. - * XSVF_SUPPORT_ERRORCODES - * This define causes the xsvfExecute function to return - * an error code for specific errors. See error codes below. - * If this is not defined, the return value defaults to the - * legacy values for backward compatibility: - * 1 = success; 0 = failure. - * Debugging: DEBUG_MODE (Legacy name) - * Define DEBUG_MODE to compile with debugging features. - * Both micro.c and ports.c must be compiled with the DEBUG_MODE - * defined to enable the standalone main implementation in - * micro.c that reads XSVF from a file. - * History: v2.00 - Original XSVF implementation. - * v4.04 - Added delay at end of XSIR for XC18v00 support. - * Added new commands for CoolRunner support: - * XSTATE, XENDIR, XENDDR - * v4.05 - Cleanup micro.c but leave ports.c intact. - * v4.06 - Fix xsvfGotoTapState for retry transition. - * v4.07 - Update example waitTime implementations for - * compatibility with Virtex-II. - * v4.10 - Add new XSIR2 command that supports a 2-byte - * IR-length parameter for IR shifts > 255 bits. - * v4.11 - No change. Update version to match SVF2XSVF xlator. - * v4.14 - Added XCOMMENT. - * v5.00 - Improve XSTATE support. - * Added XWAIT. - *****************************************************************************/ - -#include <common.h> -#include <command.h> -#include <asm/processor.h> - -#include "micro.h" -#include "lenval.h" -#include "ports.h" - -const unsigned char *xsvfdata; - -/*============================================================================ - * XSVF #define - ============================================================================*/ - -#define XSVF_VERSION "5.00" - -/***************************************************************************** - * Define: XSVF_SUPPORT_COMPRESSION - * Description: Define this to support the XC9500/XL XSVF data compression - * scheme. - * Code size can be reduced by NOT supporting this feature. - * However, you must use the -nc (no compress) option when - * translating SVF to XSVF using the SVF2XSVF translator. - * Corresponding, uncompressed XSVF may be larger. - *****************************************************************************/ -#ifndef XSVF_SUPPORT_COMPRESSION -#define XSVF_SUPPORT_COMPRESSION 1 -#endif - -/***************************************************************************** - * Define: XSVF_SUPPORT_ERRORCODES - * Description: Define this to support the new XSVF error codes. - * (The original XSVF player just returned 1 for success and - * 0 for an unspecified failure.) - *****************************************************************************/ -#ifndef XSVF_SUPPORT_ERRORCODES -#define XSVF_SUPPORT_ERRORCODES 1 -#endif - -#ifdef XSVF_SUPPORT_ERRORCODES -#define XSVF_ERRORCODE(errorCode) errorCode -#else /* Use legacy error code */ -#define XSVF_ERRORCODE(errorCode) ((errorCode==XSVF_ERROR_NONE)?1:0) -#endif /* XSVF_SUPPORT_ERRORCODES */ - - -/*============================================================================ - * DEBUG_MODE #define - ============================================================================*/ -#define DEBUG_MODE - -#ifdef DEBUG_MODE -#define XSVFDBG_PRINTF(iDebugLevel,pzFormat) \ - { if ( xsvf_iDebugLevel >= iDebugLevel ) \ - printf( pzFormat ); } -#define XSVFDBG_PRINTF1(iDebugLevel,pzFormat,arg1) \ - { if ( xsvf_iDebugLevel >= iDebugLevel ) \ - printf( pzFormat, arg1 ); } -#define XSVFDBG_PRINTF2(iDebugLevel,pzFormat,arg1,arg2) \ - { if ( xsvf_iDebugLevel >= iDebugLevel ) \ - printf( pzFormat, arg1, arg2 ); } -#define XSVFDBG_PRINTF3(iDebugLevel,pzFormat,arg1,arg2,arg3) \ - { if ( xsvf_iDebugLevel >= iDebugLevel ) \ - printf( pzFormat, arg1, arg2, arg3 ); } -#define XSVFDBG_PRINTLENVAL(iDebugLevel,plenVal) \ - { if ( xsvf_iDebugLevel >= iDebugLevel ) \ - xsvfPrintLenVal(plenVal); } -#else /* !DEBUG_MODE */ -#define XSVFDBG_PRINTF(iDebugLevel,pzFormat) -#define XSVFDBG_PRINTF1(iDebugLevel,pzFormat,arg1) -#define XSVFDBG_PRINTF2(iDebugLevel,pzFormat,arg1,arg2) -#define XSVFDBG_PRINTF3(iDebugLevel,pzFormat,arg1,arg2,arg3) -#define XSVFDBG_PRINTLENVAL(iDebugLevel,plenVal) -#endif /* DEBUG_MODE */ - - -/*============================================================================ - * XSVF Type Declarations - ============================================================================*/ - -/***************************************************************************** - * Struct: SXsvfInfo - * Description: This structure contains all of the data used during the - * execution of the XSVF. Some data is persistent, predefined - * information (e.g. lRunTestTime). The bulk of this struct's - * size is due to the lenVal structs (defined in lenval.h) - * which contain buffers for the active shift data. The MAX_LEN - * #define in lenval.h defines the size of these buffers. - * These buffers must be large enough to store the longest - * shift data in your XSVF file. For example: - * MAX_LEN >= ( longest_shift_data_in_bits / 8 ) - * Because the lenVal struct dominates the space usage of this - * struct, the rough size of this struct is: - * sizeof( SXsvfInfo ) ~= MAX_LEN * 7 (number of lenVals) - * xsvfInitialize() contains initialization code for the data - * in this struct. - * xsvfCleanup() contains cleanup code for the data in this - * struct. - *****************************************************************************/ -typedef struct tagSXsvfInfo -{ - /* XSVF status information */ - unsigned char ucComplete; /* 0 = running; 1 = complete */ - unsigned char ucCommand; /* Current XSVF command byte */ - long lCommandCount; /* Number of commands processed */ - int iErrorCode; /* An error code. 0 = no error. */ - - /* TAP state/sequencing information */ - unsigned char ucTapState; /* Current TAP state */ - unsigned char ucEndIR; /* ENDIR TAP state (See SVF) */ - unsigned char ucEndDR; /* ENDDR TAP state (See SVF) */ - - /* RUNTEST information */ - unsigned char ucMaxRepeat; /* Max repeat loops (for xc9500/xl) */ - long lRunTestTime; /* Pre-specified RUNTEST time (usec) */ - - /* Shift Data Info and Buffers */ - long lShiftLengthBits; /* Len. current shift data in bits */ - short sShiftLengthBytes; /* Len. current shift data in bytes */ - - lenVal lvTdi; /* Current TDI shift data */ - lenVal lvTdoExpected; /* Expected TDO shift data */ - lenVal lvTdoCaptured; /* Captured TDO shift data */ - lenVal lvTdoMask; /* TDO mask: 0=dontcare; 1=compare */ - -#ifdef XSVF_SUPPORT_COMPRESSION - /* XSDRINC Data Buffers */ - lenVal lvAddressMask; /* Address mask for XSDRINC */ - lenVal lvDataMask; /* Data mask for XSDRINC */ - lenVal lvNextData; /* Next data for XSDRINC */ -#endif /* XSVF_SUPPORT_COMPRESSION */ -} SXsvfInfo; - -/* Declare pointer to functions that perform XSVF commands */ -typedef int (*TXsvfDoCmdFuncPtr)( SXsvfInfo* ); - -/*============================================================================ - * XSVF Command Bytes - ============================================================================*/ - -/* encodings of xsvf instructions */ -#define XCOMPLETE 0 -#define XTDOMASK 1 -#define XSIR 2 -#define XSDR 3 -#define XRUNTEST 4 -/* Reserved 5 */ -/* Reserved 6 */ -#define XREPEAT 7 -#define XSDRSIZE 8 -#define XSDRTDO 9 -#define XSETSDRMASKS 10 -#define XSDRINC 11 -#define XSDRB 12 -#define XSDRC 13 -#define XSDRE 14 -#define XSDRTDOB 15 -#define XSDRTDOC 16 -#define XSDRTDOE 17 -#define XSTATE 18 /* 4.00 */ -#define XENDIR 19 /* 4.04 */ -#define XENDDR 20 /* 4.04 */ -#define XSIR2 21 /* 4.10 */ -#define XCOMMENT 22 /* 4.14 */ -#define XWAIT 23 /* 5.00 */ -/* Insert new commands here */ -/* and add corresponding xsvfDoCmd function to xsvf_pfDoCmd below. */ -#define XLASTCMD 24 /* Last command marker */ - - -/*============================================================================ - * XSVF Command Parameter Values - ============================================================================*/ - -#define XSTATE_RESET 0 /* 4.00 parameter for XSTATE */ -#define XSTATE_RUNTEST 1 /* 4.00 parameter for XSTATE */ - -#define XENDXR_RUNTEST 0 /* 4.04 parameter for XENDIR/DR */ -#define XENDXR_PAUSE 1 /* 4.04 parameter for XENDIR/DR */ - -/* TAP states */ -#define XTAPSTATE_RESET 0x00 -#define XTAPSTATE_RUNTEST 0x01 /* a.k.a. IDLE */ -#define XTAPSTATE_SELECTDR 0x02 -#define XTAPSTATE_CAPTUREDR 0x03 -#define XTAPSTATE_SHIFTDR 0x04 -#define XTAPSTATE_EXIT1DR 0x05 -#define XTAPSTATE_PAUSEDR 0x06 -#define XTAPSTATE_EXIT2DR 0x07 -#define XTAPSTATE_UPDATEDR 0x08 -#define XTAPSTATE_IRSTATES 0x09 /* All IR states begin here */ -#define XTAPSTATE_SELECTIR 0x09 -#define XTAPSTATE_CAPTUREIR 0x0A -#define XTAPSTATE_SHIFTIR 0x0B -#define XTAPSTATE_EXIT1IR 0x0C -#define XTAPSTATE_PAUSEIR 0x0D -#define XTAPSTATE_EXIT2IR 0x0E -#define XTAPSTATE_UPDATEIR 0x0F - -/*============================================================================ - * XSVF Function Prototypes - ============================================================================*/ - -int xsvfDoIllegalCmd( SXsvfInfo* pXsvfInfo ); /* Illegal command function */ -int xsvfDoXCOMPLETE( SXsvfInfo* pXsvfInfo ); -int xsvfDoXTDOMASK( SXsvfInfo* pXsvfInfo ); -int xsvfDoXSIR( SXsvfInfo* pXsvfInfo ); -int xsvfDoXSIR2( SXsvfInfo* pXsvfInfo ); -int xsvfDoXSDR( SXsvfInfo* pXsvfInfo ); -int xsvfDoXRUNTEST( SXsvfInfo* pXsvfInfo ); -int xsvfDoXREPEAT( SXsvfInfo* pXsvfInfo ); -int xsvfDoXSDRSIZE( SXsvfInfo* pXsvfInfo ); -int xsvfDoXSDRTDO( SXsvfInfo* pXsvfInfo ); -int xsvfDoXSETSDRMASKS( SXsvfInfo* pXsvfInfo ); -int xsvfDoXSDRINC( SXsvfInfo* pXsvfInfo ); -int xsvfDoXSDRBCE( SXsvfInfo* pXsvfInfo ); -int xsvfDoXSDRTDOBCE( SXsvfInfo* pXsvfInfo ); -int xsvfDoXSTATE( SXsvfInfo* pXsvfInfo ); -int xsvfDoXENDXR( SXsvfInfo* pXsvfInfo ); -int xsvfDoXCOMMENT( SXsvfInfo* pXsvfInfo ); -int xsvfDoXWAIT( SXsvfInfo* pXsvfInfo ); -/* Insert new command functions here */ - -/*============================================================================ - * XSVF Global Variables - ============================================================================*/ - -/* Array of XSVF command functions. Must follow command byte value order! */ -/* If your compiler cannot take this form, then convert to a switch statement*/ -TXsvfDoCmdFuncPtr xsvf_pfDoCmd[] = -{ - xsvfDoXCOMPLETE, /* 0 */ - xsvfDoXTDOMASK, /* 1 */ - xsvfDoXSIR, /* 2 */ - xsvfDoXSDR, /* 3 */ - xsvfDoXRUNTEST, /* 4 */ - xsvfDoIllegalCmd, /* 5 */ - xsvfDoIllegalCmd, /* 6 */ - xsvfDoXREPEAT, /* 7 */ - xsvfDoXSDRSIZE, /* 8 */ - xsvfDoXSDRTDO, /* 9 */ -#ifdef XSVF_SUPPORT_COMPRESSION - xsvfDoXSETSDRMASKS, /* 10 */ - xsvfDoXSDRINC, /* 11 */ -#else - xsvfDoIllegalCmd, /* 10 */ - xsvfDoIllegalCmd, /* 11 */ -#endif /* XSVF_SUPPORT_COMPRESSION */ - xsvfDoXSDRBCE, /* 12 */ - xsvfDoXSDRBCE, /* 13 */ - xsvfDoXSDRBCE, /* 14 */ - xsvfDoXSDRTDOBCE, /* 15 */ - xsvfDoXSDRTDOBCE, /* 16 */ - xsvfDoXSDRTDOBCE, /* 17 */ - xsvfDoXSTATE, /* 18 */ - xsvfDoXENDXR, /* 19 */ - xsvfDoXENDXR, /* 20 */ - xsvfDoXSIR2, /* 21 */ - xsvfDoXCOMMENT, /* 22 */ - xsvfDoXWAIT /* 23 */ -/* Insert new command functions here */ -}; - -#ifdef DEBUG_MODE -char* xsvf_pzCommandName[] = -{ - "XCOMPLETE", - "XTDOMASK", - "XSIR", - "XSDR", - "XRUNTEST", - "Reserved5", - "Reserved6", - "XREPEAT", - "XSDRSIZE", - "XSDRTDO", - "XSETSDRMASKS", - "XSDRINC", - "XSDRB", - "XSDRC", - "XSDRE", - "XSDRTDOB", - "XSDRTDOC", - "XSDRTDOE", - "XSTATE", - "XENDIR", - "XENDDR", - "XSIR2", - "XCOMMENT", - "XWAIT" -}; - -char* xsvf_pzErrorName[] = -{ - "No error", - "ERROR: Unknown", - "ERROR: TDO mismatch", - "ERROR: TDO mismatch and exceeded max retries", - "ERROR: Unsupported XSVF command", - "ERROR: Illegal state specification", - "ERROR: Data overflows allocated MAX_LEN buffer size" -}; - -char* xsvf_pzTapState[] = -{ - "RESET", /* 0x00 */ - "RUNTEST/IDLE", /* 0x01 */ - "DRSELECT", /* 0x02 */ - "DRCAPTURE", /* 0x03 */ - "DRSHIFT", /* 0x04 */ - "DREXIT1", /* 0x05 */ - "DRPAUSE", /* 0x06 */ - "DREXIT2", /* 0x07 */ - "DRUPDATE", /* 0x08 */ - "IRSELECT", /* 0x09 */ - "IRCAPTURE", /* 0x0A */ - "IRSHIFT", /* 0x0B */ - "IREXIT1", /* 0x0C */ - "IRPAUSE", /* 0x0D */ - "IREXIT2", /* 0x0E */ - "IRUPDATE" /* 0x0F */ -}; -#endif /* DEBUG_MODE */ - -/*#ifdef DEBUG_MODE */ -/* FILE* in; /XXX* Legacy DEBUG_MODE file pointer */ -int xsvf_iDebugLevel; -/*#endif /XXX* DEBUG_MODE */ - -/*============================================================================ - * Utility Functions - ============================================================================*/ - -/***************************************************************************** - * Function: xsvfPrintLenVal - * Description: Print the lenval value in hex. - * Parameters: plv - ptr to lenval. - * Returns: void. - *****************************************************************************/ -#ifdef DEBUG_MODE -void xsvfPrintLenVal( lenVal *plv ) -{ - int i; - - if ( plv ) - { - printf( "0x" ); - for ( i = 0; i < plv->len; ++i ) - { - printf( "%02x", ((unsigned int)(plv->val[ i ])) ); - } - } -} -#endif /* DEBUG_MODE */ - - -/***************************************************************************** - * Function: xsvfInfoInit - * Description: Initialize the xsvfInfo data. - * Parameters: pXsvfInfo - ptr to the XSVF info structure. - * Returns: int - 0 = success; otherwise error. - *****************************************************************************/ -int xsvfInfoInit( SXsvfInfo* pXsvfInfo ) -{ - XSVFDBG_PRINTF1( 4, " sizeof( SXsvfInfo ) = %d bytes\n", - sizeof( SXsvfInfo ) ); - - pXsvfInfo->ucComplete = 0; - pXsvfInfo->ucCommand = XCOMPLETE; - pXsvfInfo->lCommandCount = 0; - pXsvfInfo->iErrorCode = XSVF_ERROR_NONE; - pXsvfInfo->ucMaxRepeat = 0; - pXsvfInfo->ucTapState = XTAPSTATE_RESET; - pXsvfInfo->ucEndIR = XTAPSTATE_RUNTEST; - pXsvfInfo->ucEndDR = XTAPSTATE_RUNTEST; - pXsvfInfo->lShiftLengthBits = 0L; - pXsvfInfo->sShiftLengthBytes= 0; - pXsvfInfo->lRunTestTime = 0L; - - return( 0 ); -} - -/***************************************************************************** - * Function: xsvfInfoCleanup - * Description: Cleanup the xsvfInfo data. - * Parameters: pXsvfInfo - ptr to the XSVF info structure. - * Returns: void. - *****************************************************************************/ -void xsvfInfoCleanup( SXsvfInfo* pXsvfInfo ) -{ -} - -/***************************************************************************** - * Function: xsvfGetAsNumBytes - * Description: Calculate the number of bytes the given number of bits - * consumes. - * Parameters: lNumBits - the number of bits. - * Returns: short - the number of bytes to store the number of bits. - *****************************************************************************/ -short xsvfGetAsNumBytes( long lNumBits ) -{ - return( (short)( ( lNumBits + 7L ) / 8L ) ); -} - -/***************************************************************************** - * Function: xsvfTmsTransition - * Description: Apply TMS and transition TAP controller by applying one TCK - * cycle. - * Parameters: sTms - new TMS value. - * Returns: void. - *****************************************************************************/ -void xsvfTmsTransition( short sTms ) -{ - setPort( TMS, sTms ); - setPort( TCK, 0 ); - setPort( TCK, 1 ); -} - -/***************************************************************************** - * Function: xsvfGotoTapState - * Description: From the current TAP state, go to the named TAP state. - * A target state of RESET ALWAYS causes TMS reset sequence. - * All SVF standard stable state paths are supported. - * All state transitions are supported except for the following - * which cause an XSVF_ERROR_ILLEGALSTATE: - * - Target==DREXIT2; Start!=DRPAUSE - * - Target==IREXIT2; Start!=IRPAUSE - * Parameters: pucTapState - Current TAP state; returns final TAP state. - * ucTargetState - New target TAP state. - * Returns: int - 0 = success; otherwise error. - *****************************************************************************/ -int xsvfGotoTapState( unsigned char* pucTapState, - unsigned char ucTargetState ) -{ - int i; - int iErrorCode; - - iErrorCode = XSVF_ERROR_NONE; - if ( ucTargetState == XTAPSTATE_RESET ) - { - /* If RESET, always perform TMS reset sequence to reset/sync TAPs */ - xsvfTmsTransition( 1 ); - for ( i = 0; i < 5; ++i ) - { - setPort( TCK, 0 ); - setPort( TCK, 1 ); - } - *pucTapState = XTAPSTATE_RESET; - XSVFDBG_PRINTF( 3, " TMS Reset Sequence -> Test-Logic-Reset\n" ); - XSVFDBG_PRINTF1( 3, " TAP State = %s\n", - xsvf_pzTapState[ *pucTapState ] ); - } else if ( ( ucTargetState != *pucTapState ) && - ( ( ( ucTargetState == XTAPSTATE_EXIT2DR ) && ( *pucTapState != XTAPSTATE_PAUSEDR ) ) || - ( ( ucTargetState == XTAPSTATE_EXIT2IR ) && ( *pucTapState != XTAPSTATE_PAUSEIR ) ) ) ) - { - /* Trap illegal TAP state path specification */ - iErrorCode = XSVF_ERROR_ILLEGALSTATE; - } else { - if ( ucTargetState == *pucTapState ) - { - /* Already in target state. Do nothing except when in DRPAUSE - or in IRPAUSE to comply with SVF standard */ - if ( ucTargetState == XTAPSTATE_PAUSEDR ) - { - xsvfTmsTransition( 1 ); - *pucTapState = XTAPSTATE_EXIT2DR; - XSVFDBG_PRINTF1( 3, " TAP State = %s\n", - xsvf_pzTapState[ *pucTapState ] ); - } - else if ( ucTargetState == XTAPSTATE_PAUSEIR ) - { - xsvfTmsTransition( 1 ); - *pucTapState = XTAPSTATE_EXIT2IR; - XSVFDBG_PRINTF1( 3, " TAP State = %s\n", - xsvf_pzTapState[ *pucTapState ] ); - } - } - - /* Perform TAP state transitions to get to the target state */ - while ( ucTargetState != *pucTapState ) - { - switch ( *pucTapState ) - { - case XTAPSTATE_RESET: - xsvfTmsTransition( 0 ); - *pucTapState = XTAPSTATE_RUNTEST; - break; - case XTAPSTATE_RUNTEST: - xsvfTmsTransition( 1 ); - *pucTapState = XTAPSTATE_SELECTDR; - break; - case XTAPSTATE_SELECTDR: - if ( ucTargetState >= XTAPSTATE_IRSTATES ) - { - xsvfTmsTransition( 1 ); - *pucTapState = XTAPSTATE_SELECTIR; - } - else - { - xsvfTmsTransition( 0 ); - *pucTapState = XTAPSTATE_CAPTUREDR; - } - break; - case XTAPSTATE_CAPTUREDR: - if ( ucTargetState == XTAPSTATE_SHIFTDR ) - { - xsvfTmsTransition( 0 ); - *pucTapState = XTAPSTATE_SHIFTDR; - } - else - { - xsvfTmsTransition( 1 ); - *pucTapState = XTAPSTATE_EXIT1DR; - } - break; - case XTAPSTATE_SHIFTDR: - xsvfTmsTransition( 1 ); - *pucTapState = XTAPSTATE_EXIT1DR; - break; - case XTAPSTATE_EXIT1DR: - if ( ucTargetState == XTAPSTATE_PAUSEDR ) - { - xsvfTmsTransition( 0 ); - *pucTapState = XTAPSTATE_PAUSEDR; - } - else - { - xsvfTmsTransition( 1 ); - *pucTapState = XTAPSTATE_UPDATEDR; - } - break; - case XTAPSTATE_PAUSEDR: - xsvfTmsTransition( 1 ); - *pucTapState = XTAPSTATE_EXIT2DR; - break; - case XTAPSTATE_EXIT2DR: - if ( ucTargetState == XTAPSTATE_SHIFTDR ) - { - xsvfTmsTransition( 0 ); - *pucTapState = XTAPSTATE_SHIFTDR; - } - else - { - xsvfTmsTransition( 1 ); - *pucTapState = XTAPSTATE_UPDATEDR; - } - break; - case XTAPSTATE_UPDATEDR: - if ( ucTargetState == XTAPSTATE_RUNTEST ) - { - xsvfTmsTransition( 0 ); - *pucTapState = XTAPSTATE_RUNTEST; - } - else - { - xsvfTmsTransition( 1 ); - *pucTapState = XTAPSTATE_SELECTDR; - } - break; - case XTAPSTATE_SELECTIR: - xsvfTmsTransition( 0 ); - *pucTapState = XTAPSTATE_CAPTUREIR; - break; - case XTAPSTATE_CAPTUREIR: - if ( ucTargetState == XTAPSTATE_SHIFTIR ) - { - xsvfTmsTransition( 0 ); - *pucTapState = XTAPSTATE_SHIFTIR; - } - else - { - xsvfTmsTransition( 1 ); - *pucTapState = XTAPSTATE_EXIT1IR; - } - break; - case XTAPSTATE_SHIFTIR: - xsvfTmsTransition( 1 ); - *pucTapState = XTAPSTATE_EXIT1IR; - break; - case XTAPSTATE_EXIT1IR: - if ( ucTargetState == XTAPSTATE_PAUSEIR ) - { - xsvfTmsTransition( 0 ); - *pucTapState = XTAPSTATE_PAUSEIR; - } - else - { - xsvfTmsTransition( 1 ); - *pucTapState = XTAPSTATE_UPDATEIR; - } - break; - case XTAPSTATE_PAUSEIR: - xsvfTmsTransition( 1 ); - *pucTapState = XTAPSTATE_EXIT2IR; - break; - case XTAPSTATE_EXIT2IR: - if ( ucTargetState == XTAPSTATE_SHIFTIR ) - { - xsvfTmsTransition( 0 ); - *pucTapState = XTAPSTATE_SHIFTIR; - } - else - { - xsvfTmsTransition( 1 ); - *pucTapState = XTAPSTATE_UPDATEIR; - } - break; - case XTAPSTATE_UPDATEIR: - if ( ucTargetState == XTAPSTATE_RUNTEST ) - { - xsvfTmsTransition( 0 ); - *pucTapState = XTAPSTATE_RUNTEST; - } - else - { - xsvfTmsTransition( 1 ); - *pucTapState = XTAPSTATE_SELECTDR; - } - break; - default: - iErrorCode = XSVF_ERROR_ILLEGALSTATE; - *pucTapState = ucTargetState; /* Exit while loop */ - break; - } - XSVFDBG_PRINTF1( 3, " TAP State = %s\n", - xsvf_pzTapState[ *pucTapState ] ); - } - } - - return( iErrorCode ); -} - -/***************************************************************************** - * Function: xsvfShiftOnly - * Description: Assumes that starting TAP state is SHIFT-DR or SHIFT-IR. - * Shift the given TDI data into the JTAG scan chain. - * Optionally, save the TDO data shifted out of the scan chain. - * Last shift cycle is special: capture last TDO, set last TDI, - * but does not pulse TCK. Caller must pulse TCK and optionally - * set TMS=1 to exit shift state. - * Parameters: lNumBits - number of bits to shift. - * plvTdi - ptr to lenval for TDI data. - * plvTdoCaptured - ptr to lenval for storing captured TDO data. - * iExitShift - 1=exit at end of shift; 0=stay in Shift-DR. - * Returns: void. - *****************************************************************************/ -void xsvfShiftOnly( long lNumBits, - lenVal* plvTdi, - lenVal* plvTdoCaptured, - int iExitShift ) -{ - unsigned char* pucTdi; - unsigned char* pucTdo; - unsigned char ucTdiByte; - unsigned char ucTdoByte; - unsigned char ucTdoBit; - int i; - - /* assert( ( ( lNumBits + 7 ) / 8 ) == plvTdi->len ); */ - - /* Initialize TDO storage len == TDI len */ - pucTdo = 0; - if ( plvTdoCaptured ) - { - plvTdoCaptured->len = plvTdi->len; - pucTdo = plvTdoCaptured->val + plvTdi->len; - } - - /* Shift LSB first. val[N-1] == LSB. val[0] == MSB. */ - pucTdi = plvTdi->val + plvTdi->len; - while ( lNumBits ) - { - /* Process on a byte-basis */ - ucTdiByte = (*(--pucTdi)); - ucTdoByte = 0; - for ( i = 0; ( lNumBits && ( i < 8 ) ); ++i ) - { - --lNumBits; - if ( iExitShift && !lNumBits ) - { - /* Exit Shift-DR state */ - setPort( TMS, 1 ); - } - - /* Set the new TDI value */ - setPort( TDI, (short)(ucTdiByte & 1) ); - ucTdiByte >>= 1; - - /* Set TCK low */ - setPort( TCK, 0 ); - - if ( pucTdo ) - { - /* Save the TDO value */ - ucTdoBit = readTDOBit(); - ucTdoByte |= ( ucTdoBit << i ); - } - - /* Set TCK high */ - setPort( TCK, 1 ); - } - - /* Save the TDO byte value */ - if ( pucTdo ) - { - (*(--pucTdo)) = ucTdoByte; - } - } -} - -/***************************************************************************** - * Function: xsvfShift - * Description: Goes to the given starting TAP state. - * Calls xsvfShiftOnly to shift in the given TDI data and - * optionally capture the TDO data. - * Compares the TDO captured data against the TDO expected - * data. - * If a data mismatch occurs, then executes the exception - * handling loop upto ucMaxRepeat times. - * Parameters: pucTapState - Ptr to current TAP state. - * ucStartState - Starting shift state: Shift-DR or Shift-IR. - * lNumBits - number of bits to shift. - * plvTdi - ptr to lenval for TDI data. - * plvTdoCaptured - ptr to lenval for storing TDO data. - * plvTdoExpected - ptr to expected TDO data. - * plvTdoMask - ptr to TDO mask. - * ucEndState - state in which to end the shift. - * lRunTestTime - amount of time to wait after the shift. - * ucMaxRepeat - Maximum number of retries on TDO mismatch. - * Returns: int - 0 = success; otherwise TDO mismatch. - * Notes: XC9500XL-only Optimization: - * Skip the waitTime() if plvTdoMask->val[0:plvTdoMask->len-1] - * is NOT all zeros and sMatch==1. - *****************************************************************************/ -int xsvfShift( unsigned char* pucTapState, - unsigned char ucStartState, - long lNumBits, - lenVal* plvTdi, - lenVal* plvTdoCaptured, - lenVal* plvTdoExpected, - lenVal* plvTdoMask, - unsigned char ucEndState, - long lRunTestTime, - unsigned char ucMaxRepeat ) -{ - int iErrorCode; - int iMismatch; - unsigned char ucRepeat; - int iExitShift; - - iErrorCode = XSVF_ERROR_NONE; - iMismatch = 0; - ucRepeat = 0; - iExitShift = ( ucStartState != ucEndState ); - - XSVFDBG_PRINTF1( 3, " Shift Length = %ld\n", lNumBits ); - XSVFDBG_PRINTF( 4, " TDI = "); - XSVFDBG_PRINTLENVAL( 4, plvTdi ); - XSVFDBG_PRINTF( 4, "\n"); - XSVFDBG_PRINTF( 4, " TDO Expected = "); - XSVFDBG_PRINTLENVAL( 4, plvTdoExpected ); - XSVFDBG_PRINTF( 4, "\n"); - - if ( !lNumBits ) - { - /* Compatibility with XSVF2.00: XSDR 0 = no shift, but wait in RTI */ - if ( lRunTestTime ) - { - /* Wait for prespecified XRUNTEST time */ - xsvfGotoTapState( pucTapState, XTAPSTATE_RUNTEST ); - XSVFDBG_PRINTF1( 3, " Wait = %ld usec\n", lRunTestTime ); - waitTime( lRunTestTime ); - } - } - else - { - do - { - /* Goto Shift-DR or Shift-IR */ - xsvfGotoTapState( pucTapState, ucStartState ); - - /* Shift TDI and capture TDO */ - xsvfShiftOnly( lNumBits, plvTdi, plvTdoCaptured, iExitShift ); - - if ( plvTdoExpected ) - { - /* Compare TDO data to expected TDO data */ - iMismatch = !EqualLenVal( plvTdoExpected, - plvTdoCaptured, - plvTdoMask ); - } - - if ( iExitShift ) - { - /* Update TAP state: Shift->Exit */ - ++(*pucTapState); - XSVFDBG_PRINTF1( 3, " TAP State = %s\n", - xsvf_pzTapState[ *pucTapState ] ); - - if ( iMismatch && lRunTestTime && ( ucRepeat < ucMaxRepeat ) ) - { - XSVFDBG_PRINTF( 4, " TDO Expected = "); - XSVFDBG_PRINTLENVAL( 4, plvTdoExpected ); - XSVFDBG_PRINTF( 4, "\n"); - XSVFDBG_PRINTF( 4, " TDO Captured = "); - XSVFDBG_PRINTLENVAL( 4, plvTdoCaptured ); - XSVFDBG_PRINTF( 4, "\n"); - XSVFDBG_PRINTF( 4, " TDO Mask = "); - XSVFDBG_PRINTLENVAL( 4, plvTdoMask ); - XSVFDBG_PRINTF( 4, "\n"); - XSVFDBG_PRINTF1( 3, " Retry #%d\n", ( ucRepeat + 1 ) ); - /* Do exception handling retry - ShiftDR only */ - xsvfGotoTapState( pucTapState, XTAPSTATE_PAUSEDR ); - /* Shift 1 extra bit */ - xsvfGotoTapState( pucTapState, XTAPSTATE_SHIFTDR ); - /* Increment RUNTEST time by an additional 25% */ - lRunTestTime += ( lRunTestTime >> 2 ); - } - else - { - /* Do normal exit from Shift-XR */ - xsvfGotoTapState( pucTapState, ucEndState ); - } - - if ( lRunTestTime ) - { - /* Wait for prespecified XRUNTEST time */ - xsvfGotoTapState( pucTapState, XTAPSTATE_RUNTEST ); - XSVFDBG_PRINTF1( 3, " Wait = %ld usec\n", lRunTestTime ); - waitTime( lRunTestTime ); - } - } - } while ( iMismatch && ( ucRepeat++ < ucMaxRepeat ) ); - } - - if ( iMismatch ) - { - XSVFDBG_PRINTF( 1, " TDO Expected = "); - XSVFDBG_PRINTLENVAL( 1, plvTdoExpected ); - XSVFDBG_PRINTF( 1, "\n"); - XSVFDBG_PRINTF( 1, " TDO Captured = "); - XSVFDBG_PRINTLENVAL( 1, plvTdoCaptured ); - XSVFDBG_PRINTF( 1, "\n"); - XSVFDBG_PRINTF( 1, " TDO Mask = "); - XSVFDBG_PRINTLENVAL( 1, plvTdoMask ); - XSVFDBG_PRINTF( 1, "\n"); - if ( ucMaxRepeat && ( ucRepeat > ucMaxRepeat ) ) - { - iErrorCode = XSVF_ERROR_MAXRETRIES; - } - else - { - iErrorCode = XSVF_ERROR_TDOMISMATCH; - } - } - - return( iErrorCode ); -} - -/***************************************************************************** - * Function: xsvfBasicXSDRTDO - * Description: Get the XSDRTDO parameters and execute the XSDRTDO command. - * This is the common function for all XSDRTDO commands. - * Parameters: pucTapState - Current TAP state. - * lShiftLengthBits - number of bits to shift. - * sShiftLengthBytes - number of bytes to read. - * plvTdi - ptr to lenval for TDI data. - * lvTdoCaptured - ptr to lenval for storing TDO data. - * iEndState - state in which to end the shift. - * lRunTestTime - amount of time to wait after the shift. - * ucMaxRepeat - maximum xc9500/xl retries. - * Returns: int - 0 = success; otherwise TDO mismatch. - *****************************************************************************/ -int xsvfBasicXSDRTDO( unsigned char* pucTapState, - long lShiftLengthBits, - short sShiftLengthBytes, - lenVal* plvTdi, - lenVal* plvTdoCaptured, - lenVal* plvTdoExpected, - lenVal* plvTdoMask, - unsigned char ucEndState, - long lRunTestTime, - unsigned char ucMaxRepeat ) -{ - readVal( plvTdi, sShiftLengthBytes ); - if ( plvTdoExpected ) - { - readVal( plvTdoExpected, sShiftLengthBytes ); - } - return( xsvfShift( pucTapState, XTAPSTATE_SHIFTDR, lShiftLengthBits, - plvTdi, plvTdoCaptured, plvTdoExpected, plvTdoMask, - ucEndState, lRunTestTime, ucMaxRepeat ) ); -} - -/***************************************************************************** - * Function: xsvfDoSDRMasking - * Description: Update the data value with the next XSDRINC data and address. - * Example: dataVal=0x01ff, nextData=0xab, addressMask=0x0100, - * dataMask=0x00ff, should set dataVal to 0x02ab - * Parameters: plvTdi - The current TDI value. - * plvNextData - the next data value. - * plvAddressMask - the address mask. - * plvDataMask - the data mask. - * Returns: void. - *****************************************************************************/ -#ifdef XSVF_SUPPORT_COMPRESSION -void xsvfDoSDRMasking( lenVal* plvTdi, - lenVal* plvNextData, - lenVal* plvAddressMask, - lenVal* plvDataMask ) -{ - int i; - unsigned char ucTdi; - unsigned char ucTdiMask; - unsigned char ucDataMask; - unsigned char ucNextData; - unsigned char ucNextMask; - short sNextData; - - /* add the address Mask to dataVal and return as a new dataVal */ - addVal( plvTdi, plvTdi, plvAddressMask ); - - ucNextData = 0; - ucNextMask = 0; - sNextData = plvNextData->len; - for ( i = plvDataMask->len - 1; i >= 0; --i ) - { - /* Go through data mask in reverse order looking for mask (1) bits */ - ucDataMask = plvDataMask->val[ i ]; - if ( ucDataMask ) - { - /* Retrieve the corresponding TDI byte value */ - ucTdi = plvTdi->val[ i ]; - - /* For each bit in the data mask byte, look for 1's */ - ucTdiMask = 1; - while ( ucDataMask ) - { - if ( ucDataMask & 1 ) - { - if ( !ucNextMask ) - { - /* Get the next data byte */ - ucNextData = plvNextData->val[ --sNextData ]; - ucNextMask = 1; - } - - /* Set or clear the data bit according to the next data */ - if ( ucNextData & ucNextMask ) - { - ucTdi |= ucTdiMask; /* Set bit */ - } - else - { - ucTdi &= ( ~ucTdiMask ); /* Clear bit */ - } - - /* Update the next data */ - ucNextMask <<= 1; - } - ucTdiMask <<= 1; - ucDataMask >>= 1; - } - - /* Update the TDI value */ - plvTdi->val[ i ] = ucTdi; - } - } -} -#endif /* XSVF_SUPPORT_COMPRESSION */ - -/*============================================================================ - * XSVF Command Functions (type = TXsvfDoCmdFuncPtr) - * These functions update pXsvfInfo->iErrorCode only on an error. - * Otherwise, the error code is left alone. - * The function returns the error code from the function. - ============================================================================*/ - -/***************************************************************************** - * Function: xsvfDoIllegalCmd - * Description: Function place holder for illegal/unsupported commands. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -int xsvfDoIllegalCmd( SXsvfInfo* pXsvfInfo ) -{ - XSVFDBG_PRINTF2( 0, "ERROR: Encountered unsupported command #%d (%s)\n", - ((unsigned int)(pXsvfInfo->ucCommand)), - ((pXsvfInfo->ucCommand < XLASTCMD) - ? (xsvf_pzCommandName[pXsvfInfo->ucCommand]) - : "Unknown") ); - pXsvfInfo->iErrorCode = XSVF_ERROR_ILLEGALCMD; - return( pXsvfInfo->iErrorCode ); -} - -/***************************************************************************** - * Function: xsvfDoXCOMPLETE - * Description: XCOMPLETE (no parameters) - * Update complete status for XSVF player. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -int xsvfDoXCOMPLETE( SXsvfInfo* pXsvfInfo ) -{ - pXsvfInfo->ucComplete = 1; - return( XSVF_ERROR_NONE ); -} - -/***************************************************************************** - * Function: xsvfDoXTDOMASK - * Description: XTDOMASK <lenVal.TdoMask[XSDRSIZE]> - * Prespecify the TDO compare mask. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -int xsvfDoXTDOMASK( SXsvfInfo* pXsvfInfo ) -{ - readVal( &(pXsvfInfo->lvTdoMask), pXsvfInfo->sShiftLengthBytes ); - XSVFDBG_PRINTF( 4, " TDO Mask = "); - XSVFDBG_PRINTLENVAL( 4, &(pXsvfInfo->lvTdoMask) ); - XSVFDBG_PRINTF( 4, "\n"); - return( XSVF_ERROR_NONE ); -} - -/***************************************************************************** - * Function: xsvfDoXSIR - * Description: XSIR <(byte)shiftlen> <lenVal.TDI[shiftlen]> - * Get the instruction and shift the instruction into the TAP. - * If prespecified XRUNTEST!=0, goto RUNTEST and wait after - * the shift for XRUNTEST usec. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -int xsvfDoXSIR( SXsvfInfo* pXsvfInfo ) -{ - unsigned char ucShiftIrBits; - short sShiftIrBytes; - int iErrorCode; - - /* Get the shift length and store */ - readByte( &ucShiftIrBits ); - sShiftIrBytes = xsvfGetAsNumBytes( ucShiftIrBits ); - XSVFDBG_PRINTF1( 3, " XSIR length = %d\n", - ((unsigned int)ucShiftIrBits) ); - - if ( sShiftIrBytes > MAX_LEN ) - { - iErrorCode = XSVF_ERROR_DATAOVERFLOW; - } - else - { - /* Get and store instruction to shift in */ - readVal( &(pXsvfInfo->lvTdi), xsvfGetAsNumBytes( ucShiftIrBits ) ); - - /* Shift the data */ - iErrorCode = xsvfShift( &(pXsvfInfo->ucTapState), XTAPSTATE_SHIFTIR, - ucShiftIrBits, &(pXsvfInfo->lvTdi), - /*plvTdoCaptured*/0, /*plvTdoExpected*/0, - /*plvTdoMask*/0, pXsvfInfo->ucEndIR, - pXsvfInfo->lRunTestTime, /*ucMaxRepeat*/0 ); - } - - if ( iErrorCode != XSVF_ERROR_NONE ) - { - pXsvfInfo->iErrorCode = iErrorCode; - } - return( iErrorCode ); -} - -/***************************************************************************** - * Function: xsvfDoXSIR2 - * Description: XSIR <(2-byte)shiftlen> <lenVal.TDI[shiftlen]> - * Get the instruction and shift the instruction into the TAP. - * If prespecified XRUNTEST!=0, goto RUNTEST and wait after - * the shift for XRUNTEST usec. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -int xsvfDoXSIR2( SXsvfInfo* pXsvfInfo ) -{ - long lShiftIrBits; - short sShiftIrBytes; - int iErrorCode; - - /* Get the shift length and store */ - readVal( &(pXsvfInfo->lvTdi), 2 ); - lShiftIrBits = value( &(pXsvfInfo->lvTdi) ); - sShiftIrBytes = xsvfGetAsNumBytes( lShiftIrBits ); - XSVFDBG_PRINTF1( 3, " XSIR2 length = %d\n", (int)lShiftIrBits); - - if ( sShiftIrBytes > MAX_LEN ) - { - iErrorCode = XSVF_ERROR_DATAOVERFLOW; - } - else - { - /* Get and store instruction to shift in */ - readVal( &(pXsvfInfo->lvTdi), xsvfGetAsNumBytes( lShiftIrBits ) ); - - /* Shift the data */ - iErrorCode = xsvfShift( &(pXsvfInfo->ucTapState), XTAPSTATE_SHIFTIR, - lShiftIrBits, &(pXsvfInfo->lvTdi), - /*plvTdoCaptured*/0, /*plvTdoExpected*/0, - /*plvTdoMask*/0, pXsvfInfo->ucEndIR, - pXsvfInfo->lRunTestTime, /*ucMaxRepeat*/0 ); - } - - if ( iErrorCode != XSVF_ERROR_NONE ) - { - pXsvfInfo->iErrorCode = iErrorCode; - } - return( iErrorCode ); -} - -/***************************************************************************** - * Function: xsvfDoXSDR - * Description: XSDR <lenVal.TDI[XSDRSIZE]> - * Shift the given TDI data into the JTAG scan chain. - * Compare the captured TDO with the expected TDO from the - * previous XSDRTDO command using the previously specified - * XTDOMASK. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -int xsvfDoXSDR( SXsvfInfo* pXsvfInfo ) -{ - int iErrorCode; - readVal( &(pXsvfInfo->lvTdi), pXsvfInfo->sShiftLengthBytes ); - /* use TDOExpected from last XSDRTDO instruction */ - iErrorCode = xsvfShift( &(pXsvfInfo->ucTapState), XTAPSTATE_SHIFTDR, - pXsvfInfo->lShiftLengthBits, &(pXsvfInfo->lvTdi), - &(pXsvfInfo->lvTdoCaptured), - &(pXsvfInfo->lvTdoExpected), - &(pXsvfInfo->lvTdoMask), pXsvfInfo->ucEndDR, - pXsvfInfo->lRunTestTime, pXsvfInfo->ucMaxRepeat ); - if ( iErrorCode != XSVF_ERROR_NONE ) - { - pXsvfInfo->iErrorCode = iErrorCode; - } - return( iErrorCode ); -} - -/***************************************************************************** - * Function: xsvfDoXRUNTEST - * Description: XRUNTEST <uint32> - * Prespecify the XRUNTEST wait time for shift operations. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -int xsvfDoXRUNTEST( SXsvfInfo* pXsvfInfo ) -{ - readVal( &(pXsvfInfo->lvTdi), 4 ); - pXsvfInfo->lRunTestTime = value( &(pXsvfInfo->lvTdi) ); - XSVFDBG_PRINTF1( 3, " XRUNTEST = %ld\n", pXsvfInfo->lRunTestTime ); - return( XSVF_ERROR_NONE ); -} - -/***************************************************************************** - * Function: xsvfDoXREPEAT - * Description: XREPEAT <byte> - * Prespecify the maximum number of XC9500/XL retries. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -int xsvfDoXREPEAT( SXsvfInfo* pXsvfInfo ) -{ - readByte( &(pXsvfInfo->ucMaxRepeat) ); - XSVFDBG_PRINTF1( 3, " XREPEAT = %d\n", - ((unsigned int)(pXsvfInfo->ucMaxRepeat)) ); - return( XSVF_ERROR_NONE ); -} - -/***************************************************************************** - * Function: xsvfDoXSDRSIZE - * Description: XSDRSIZE <uint32> - * Prespecify the XRUNTEST wait time for shift operations. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -int xsvfDoXSDRSIZE( SXsvfInfo* pXsvfInfo ) -{ - int iErrorCode; - iErrorCode = XSVF_ERROR_NONE; - readVal( &(pXsvfInfo->lvTdi), 4 ); - pXsvfInfo->lShiftLengthBits = value( &(pXsvfInfo->lvTdi) ); - pXsvfInfo->sShiftLengthBytes= xsvfGetAsNumBytes( pXsvfInfo->lShiftLengthBits ); - XSVFDBG_PRINTF1( 3, " XSDRSIZE = %ld\n", pXsvfInfo->lShiftLengthBits ); - if ( pXsvfInfo->sShiftLengthBytes > MAX_LEN ) - { - iErrorCode = XSVF_ERROR_DATAOVERFLOW; - pXsvfInfo->iErrorCode = iErrorCode; - } - return( iErrorCode ); -} - -/***************************************************************************** - * Function: xsvfDoXSDRTDO - * Description: XSDRTDO <lenVal.TDI[XSDRSIZE]> <lenVal.TDO[XSDRSIZE]> - * Get the TDI and expected TDO values. Then, shift. - * Compare the expected TDO with the captured TDO using the - * prespecified XTDOMASK. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -int xsvfDoXSDRTDO( SXsvfInfo* pXsvfInfo ) -{ - int iErrorCode; - iErrorCode = xsvfBasicXSDRTDO( &(pXsvfInfo->ucTapState), - pXsvfInfo->lShiftLengthBits, - pXsvfInfo->sShiftLengthBytes, - &(pXsvfInfo->lvTdi), - &(pXsvfInfo->lvTdoCaptured), - &(pXsvfInfo->lvTdoExpected), - &(pXsvfInfo->lvTdoMask), - pXsvfInfo->ucEndDR, - pXsvfInfo->lRunTestTime, - pXsvfInfo->ucMaxRepeat ); - if ( iErrorCode != XSVF_ERROR_NONE ) - { - pXsvfInfo->iErrorCode = iErrorCode; - } - return( iErrorCode ); -} - -/***************************************************************************** - * Function: xsvfDoXSETSDRMASKS - * Description: XSETSDRMASKS <lenVal.AddressMask[XSDRSIZE]> - * <lenVal.DataMask[XSDRSIZE]> - * Get the prespecified address and data mask for the XSDRINC - * command. - * Used for xc9500/xl compressed XSVF data. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -#ifdef XSVF_SUPPORT_COMPRESSION -int xsvfDoXSETSDRMASKS( SXsvfInfo* pXsvfInfo ) -{ - /* read the addressMask */ - readVal( &(pXsvfInfo->lvAddressMask), pXsvfInfo->sShiftLengthBytes ); - /* read the dataMask */ - readVal( &(pXsvfInfo->lvDataMask), pXsvfInfo->sShiftLengthBytes ); - - XSVFDBG_PRINTF( 4, " Address Mask = " ); - XSVFDBG_PRINTLENVAL( 4, &(pXsvfInfo->lvAddressMask) ); - XSVFDBG_PRINTF( 4, "\n" ); - XSVFDBG_PRINTF( 4, " Data Mask = " ); - XSVFDBG_PRINTLENVAL( 4, &(pXsvfInfo->lvDataMask) ); - XSVFDBG_PRINTF( 4, "\n" ); - - return( XSVF_ERROR_NONE ); -} -#endif /* XSVF_SUPPORT_COMPRESSION */ - -/***************************************************************************** - * Function: xsvfDoXSDRINC - * Description: XSDRINC <lenVal.firstTDI[XSDRSIZE]> <byte(numTimes)> - * <lenVal.data[XSETSDRMASKS.dataMask.len]> ... - * Get the XSDRINC parameters and execute the XSDRINC command. - * XSDRINC starts by loading the first TDI shift value. - * Then, for numTimes, XSDRINC gets the next piece of data, - * replaces the bits from the starting TDI as defined by the - * XSETSDRMASKS.dataMask, adds the address mask from - * XSETSDRMASKS.addressMask, shifts the new TDI value, - * and compares the TDO to the expected TDO from the previous - * XSDRTDO command using the XTDOMASK. - * Used for xc9500/xl compressed XSVF data. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -#ifdef XSVF_SUPPORT_COMPRESSION -int xsvfDoXSDRINC( SXsvfInfo* pXsvfInfo ) -{ - int iErrorCode; - int iDataMaskLen; - unsigned char ucDataMask; - unsigned char ucNumTimes; - unsigned char i; - - readVal( &(pXsvfInfo->lvTdi), pXsvfInfo->sShiftLengthBytes ); - iErrorCode = xsvfShift( &(pXsvfInfo->ucTapState), XTAPSTATE_SHIFTDR, - pXsvfInfo->lShiftLengthBits, - &(pXsvfInfo->lvTdi), &(pXsvfInfo->lvTdoCaptured), - &(pXsvfInfo->lvTdoExpected), - &(pXsvfInfo->lvTdoMask), pXsvfInfo->ucEndDR, - pXsvfInfo->lRunTestTime, pXsvfInfo->ucMaxRepeat ); - if ( !iErrorCode ) - { - /* Calculate number of data mask bits */ - iDataMaskLen = 0; - for ( i = 0; i < pXsvfInfo->lvDataMask.len; ++i ) - { - ucDataMask = pXsvfInfo->lvDataMask.val[ i ]; - while ( ucDataMask ) - { - iDataMaskLen += ( ucDataMask & 1 ); - ucDataMask >>= 1; - } - } - - /* Get the number of data pieces, i.e. number of times to shift */ - readByte( &ucNumTimes ); - - /* For numTimes, get data, fix TDI, and shift */ - for ( i = 0; !iErrorCode && ( i < ucNumTimes ); ++i ) - { - readVal( &(pXsvfInfo->lvNextData), - xsvfGetAsNumBytes( iDataMaskLen ) ); - xsvfDoSDRMasking( &(pXsvfInfo->lvTdi), - &(pXsvfInfo->lvNextData), - &(pXsvfInfo->lvAddressMask), - &(pXsvfInfo->lvDataMask) ); - iErrorCode = xsvfShift( &(pXsvfInfo->ucTapState), - XTAPSTATE_SHIFTDR, - pXsvfInfo->lShiftLengthBits, - &(pXsvfInfo->lvTdi), - &(pXsvfInfo->lvTdoCaptured), - &(pXsvfInfo->lvTdoExpected), - &(pXsvfInfo->lvTdoMask), - pXsvfInfo->ucEndDR, - pXsvfInfo->lRunTestTime, - pXsvfInfo->ucMaxRepeat ); - } - } - if ( iErrorCode != XSVF_ERROR_NONE ) - { - pXsvfInfo->iErrorCode = iErrorCode; - } - return( iErrorCode ); -} -#endif /* XSVF_SUPPORT_COMPRESSION */ - -/***************************************************************************** - * Function: xsvfDoXSDRBCE - * Description: XSDRB/XSDRC/XSDRE <lenVal.TDI[XSDRSIZE]> - * If not already in SHIFTDR, goto SHIFTDR. - * Shift the given TDI data into the JTAG scan chain. - * Ignore TDO. - * If cmd==XSDRE, then goto ENDDR. Otherwise, stay in ShiftDR. - * XSDRB, XSDRC, and XSDRE are the same implementation. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -int xsvfDoXSDRBCE( SXsvfInfo* pXsvfInfo ) -{ - unsigned char ucEndDR; - int iErrorCode; - ucEndDR = (unsigned char)(( pXsvfInfo->ucCommand == XSDRE ) ? - pXsvfInfo->ucEndDR : XTAPSTATE_SHIFTDR); - iErrorCode = xsvfBasicXSDRTDO( &(pXsvfInfo->ucTapState), - pXsvfInfo->lShiftLengthBits, - pXsvfInfo->sShiftLengthBytes, - &(pXsvfInfo->lvTdi), - /*plvTdoCaptured*/0, /*plvTdoExpected*/0, - /*plvTdoMask*/0, ucEndDR, - /*lRunTestTime*/0, /*ucMaxRepeat*/0 ); - if ( iErrorCode != XSVF_ERROR_NONE ) - { - pXsvfInfo->iErrorCode = iErrorCode; - } - return( iErrorCode ); -} - -/***************************************************************************** - * Function: xsvfDoXSDRTDOBCE - * Description: XSDRB/XSDRC/XSDRE <lenVal.TDI[XSDRSIZE]> <lenVal.TDO[XSDRSIZE]> - * If not already in SHIFTDR, goto SHIFTDR. - * Shift the given TDI data into the JTAG scan chain. - * Compare TDO, but do NOT use XTDOMASK. - * If cmd==XSDRTDOE, then goto ENDDR. Otherwise, stay in ShiftDR. - * XSDRTDOB, XSDRTDOC, and XSDRTDOE are the same implementation. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -int xsvfDoXSDRTDOBCE( SXsvfInfo* pXsvfInfo ) -{ - unsigned char ucEndDR; - int iErrorCode; - ucEndDR = (unsigned char)(( pXsvfInfo->ucCommand == XSDRTDOE ) ? - pXsvfInfo->ucEndDR : XTAPSTATE_SHIFTDR); - iErrorCode = xsvfBasicXSDRTDO( &(pXsvfInfo->ucTapState), - pXsvfInfo->lShiftLengthBits, - pXsvfInfo->sShiftLengthBytes, - &(pXsvfInfo->lvTdi), - &(pXsvfInfo->lvTdoCaptured), - &(pXsvfInfo->lvTdoExpected), - /*plvTdoMask*/0, ucEndDR, - /*lRunTestTime*/0, /*ucMaxRepeat*/0 ); - if ( iErrorCode != XSVF_ERROR_NONE ) - { - pXsvfInfo->iErrorCode = iErrorCode; - } - return( iErrorCode ); -} - -/***************************************************************************** - * Function: xsvfDoXSTATE - * Description: XSTATE <byte> - * <byte> == XTAPSTATE; - * Get the state parameter and transition the TAP to that state. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -int xsvfDoXSTATE( SXsvfInfo* pXsvfInfo ) -{ - unsigned char ucNextState; - int iErrorCode; - readByte( &ucNextState ); - iErrorCode = xsvfGotoTapState( &(pXsvfInfo->ucTapState), ucNextState ); - if ( iErrorCode != XSVF_ERROR_NONE ) - { - pXsvfInfo->iErrorCode = iErrorCode; - } - return( iErrorCode ); -} - -/***************************************************************************** - * Function: xsvfDoXENDXR - * Description: XENDIR/XENDDR <byte> - * <byte>: 0 = RUNTEST; 1 = PAUSE. - * Get the prespecified XENDIR or XENDDR. - * Both XENDIR and XENDDR use the same implementation. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -int xsvfDoXENDXR( SXsvfInfo* pXsvfInfo ) -{ - int iErrorCode; - unsigned char ucEndState; - - iErrorCode = XSVF_ERROR_NONE; - readByte( &ucEndState ); - if ( ( ucEndState != XENDXR_RUNTEST ) && ( ucEndState != XENDXR_PAUSE ) ) - { - iErrorCode = XSVF_ERROR_ILLEGALSTATE; - } - else - { - - if ( pXsvfInfo->ucCommand == XENDIR ) - { - if ( ucEndState == XENDXR_RUNTEST ) - { - pXsvfInfo->ucEndIR = XTAPSTATE_RUNTEST; - } - else - { - pXsvfInfo->ucEndIR = XTAPSTATE_PAUSEIR; - } - XSVFDBG_PRINTF1( 3, " ENDIR State = %s\n", - xsvf_pzTapState[ pXsvfInfo->ucEndIR ] ); - } - else /* XENDDR */ - { - if ( ucEndState == XENDXR_RUNTEST ) - { - pXsvfInfo->ucEndDR = XTAPSTATE_RUNTEST; - } - else - { - pXsvfInfo->ucEndDR = XTAPSTATE_PAUSEDR; - } - XSVFDBG_PRINTF1( 3, " ENDDR State = %s\n", - xsvf_pzTapState[ pXsvfInfo->ucEndDR ] ); - } - } - - if ( iErrorCode != XSVF_ERROR_NONE ) - { - pXsvfInfo->iErrorCode = iErrorCode; - } - return( iErrorCode ); -} - -/***************************************************************************** - * Function: xsvfDoXCOMMENT - * Description: XCOMMENT <text string ending in \0> - * <text string ending in \0> == text comment; - * Arbitrary comment embedded in the XSVF. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -int xsvfDoXCOMMENT( SXsvfInfo* pXsvfInfo ) -{ - /* Use the comment for debugging */ - /* Otherwise, read through the comment to the end '\0' and ignore */ - unsigned char ucText; - - if ( xsvf_iDebugLevel > 0 ) - { - putc( ' ' ); - } - - do - { - readByte( &ucText ); - if ( xsvf_iDebugLevel > 0 ) - { - putc( ucText ? ucText : '\n' ); - } - } while ( ucText ); - - pXsvfInfo->iErrorCode = XSVF_ERROR_NONE; - - return( pXsvfInfo->iErrorCode ); -} - -/***************************************************************************** - * Function: xsvfDoXWAIT - * Description: XWAIT <wait_state> <end_state> <wait_time> - * If not already in <wait_state>, then go to <wait_state>. - * Wait in <wait_state> for <wait_time> microseconds. - * Finally, if not already in <end_state>, then goto <end_state>. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -int xsvfDoXWAIT( SXsvfInfo* pXsvfInfo ) -{ - unsigned char ucWaitState; - unsigned char ucEndState; - long lWaitTime; - - /* Get Parameters */ - /* <wait_state> */ - readVal( &(pXsvfInfo->lvTdi), 1 ); - ucWaitState = pXsvfInfo->lvTdi.val[0]; - - /* <end_state> */ - readVal( &(pXsvfInfo->lvTdi), 1 ); - ucEndState = pXsvfInfo->lvTdi.val[0]; - - /* <wait_time> */ - readVal( &(pXsvfInfo->lvTdi), 4 ); - lWaitTime = value( &(pXsvfInfo->lvTdi) ); - XSVFDBG_PRINTF2( 3, " XWAIT: state = %s; time = %ld\n", - xsvf_pzTapState[ ucWaitState ], lWaitTime ); - - /* If not already in <wait_state>, go to <wait_state> */ - if ( pXsvfInfo->ucTapState != ucWaitState ) - { - xsvfGotoTapState( &(pXsvfInfo->ucTapState), ucWaitState ); - } - - /* Wait for <wait_time> microseconds */ - waitTime( lWaitTime ); - - /* If not already in <end_state>, go to <end_state> */ - if ( pXsvfInfo->ucTapState != ucEndState ) - { - xsvfGotoTapState( &(pXsvfInfo->ucTapState), ucEndState ); - } - - return( XSVF_ERROR_NONE ); -} - - -/*============================================================================ - * Execution Control Functions - ============================================================================*/ - -/***************************************************************************** - * Function: xsvfInitialize - * Description: Initialize the xsvf player. - * Call this before running the player to initialize the data - * in the SXsvfInfo struct. - * xsvfCleanup is called to clean up the data in SXsvfInfo - * after the XSVF is played. - * Parameters: pXsvfInfo - ptr to the XSVF information. - * Returns: int - 0 = success; otherwise error. - *****************************************************************************/ -int xsvfInitialize( SXsvfInfo* pXsvfInfo ) -{ - /* Initialize values */ - pXsvfInfo->iErrorCode = xsvfInfoInit( pXsvfInfo ); - - if ( !pXsvfInfo->iErrorCode ) - { - /* Initialize the TAPs */ - pXsvfInfo->iErrorCode = xsvfGotoTapState( &(pXsvfInfo->ucTapState), - XTAPSTATE_RESET ); - } - - return( pXsvfInfo->iErrorCode ); -} - -/***************************************************************************** - * Function: xsvfRun - * Description: Run the xsvf player for a single command and return. - * First, call xsvfInitialize. - * Then, repeatedly call this function until an error is detected - * or until the pXsvfInfo->ucComplete variable is non-zero. - * Finally, call xsvfCleanup to cleanup any remnants. - * Parameters: pXsvfInfo - ptr to the XSVF information. - * Returns: int - 0 = success; otherwise error. - *****************************************************************************/ -int xsvfRun( SXsvfInfo* pXsvfInfo ) -{ - /* Process the XSVF commands */ - if ( (!pXsvfInfo->iErrorCode) && (!pXsvfInfo->ucComplete) ) - { - /* read 1 byte for the instruction */ - readByte( &(pXsvfInfo->ucCommand) ); - ++(pXsvfInfo->lCommandCount); - - if ( pXsvfInfo->ucCommand < XLASTCMD ) - { - /* Execute the command. Func sets error code. */ - XSVFDBG_PRINTF1( 2, " %s\n", - xsvf_pzCommandName[pXsvfInfo->ucCommand] ); - /* If your compiler cannot take this form, - then convert to a switch statement */ -#if 0 /* test-only */ - xsvf_pfDoCmd[ pXsvfInfo->ucCommand ]( pXsvfInfo ); -#else - switch (pXsvfInfo->ucCommand) { - case 0: - xsvfDoXCOMPLETE(pXsvfInfo); /* 0 */ - break; - case 1: - xsvfDoXTDOMASK(pXsvfInfo); /* 1 */ - break; - case 2: - xsvfDoXSIR(pXsvfInfo); /* 2 */ - break; - case 3: - xsvfDoXSDR(pXsvfInfo); /* 3 */ - break; - case 4: - xsvfDoXRUNTEST(pXsvfInfo); /* 4 */ - break; - case 5: - xsvfDoIllegalCmd(pXsvfInfo); /* 5 */ - break; - case 6: - xsvfDoIllegalCmd(pXsvfInfo); /* 6 */ - break; - case 7: - xsvfDoXREPEAT(pXsvfInfo); /* 7 */ - break; - case 8: - xsvfDoXSDRSIZE(pXsvfInfo); /* 8 */ - break; - case 9: - xsvfDoXSDRTDO(pXsvfInfo); /* 9 */ - break; -#ifdef XSVF_SUPPORT_COMPRESSION - case 10: - xsvfDoXSETSDRMASKS(pXsvfInfo); /* 10 */ - break; - case 11: - xsvfDoXSDRINC(pXsvfInfo); /* 11 */ - break; -#else - case 10: - xsvfDoIllegalCmd(pXsvfInfo); /* 10 */ - break; - case 11: - xsvfDoIllegalCmd(pXsvfInfo); /* 11 */ - break; -#endif /* XSVF_SUPPORT_COMPRESSION */ - case 12: - xsvfDoXSDRBCE(pXsvfInfo); /* 12 */ - break; - case 13: - xsvfDoXSDRBCE(pXsvfInfo); /* 13 */ - break; - case 14: - xsvfDoXSDRBCE(pXsvfInfo); /* 14 */ - break; - case 15: - xsvfDoXSDRTDOBCE(pXsvfInfo); /* 15 */ - break; - case 16: - xsvfDoXSDRTDOBCE(pXsvfInfo); /* 16 */ - break; - case 17: - xsvfDoXSDRTDOBCE(pXsvfInfo); /* 17 */ - break; - case 18: - xsvfDoXSTATE(pXsvfInfo); /* 18 */ - break; - case 19: - xsvfDoXENDXR(pXsvfInfo); /* 19 */ - break; - case 20: - xsvfDoXENDXR(pXsvfInfo); /* 20 */ - break; - case 21: - xsvfDoXSIR2(pXsvfInfo); /* 21 */ - break; - case 22: - xsvfDoXCOMMENT(pXsvfInfo); /* 22 */ - break; - case 23: - xsvfDoXWAIT(pXsvfInfo); /* 23 */ - break; - } -#endif - } - else - { - /* Illegal command value. Func sets error code. */ - xsvfDoIllegalCmd( pXsvfInfo ); - } - } - - return( pXsvfInfo->iErrorCode ); -} - -/***************************************************************************** - * Function: xsvfCleanup - * Description: cleanup remnants of the xsvf player. - * Parameters: pXsvfInfo - ptr to the XSVF information. - * Returns: void. - *****************************************************************************/ -void xsvfCleanup( SXsvfInfo* pXsvfInfo ) -{ - xsvfInfoCleanup( pXsvfInfo ); -} - - -/*============================================================================ - * xsvfExecute() - The primary entry point to the XSVF player - ============================================================================*/ - -/***************************************************************************** - * Function: xsvfExecute - * Description: Process, interpret, and apply the XSVF commands. - * See port.c:readByte for source of XSVF data. - * Parameters: none. - * Returns: int - Legacy result values: 1 == success; 0 == failed. - *****************************************************************************/ -int xsvfExecute(void) -{ - SXsvfInfo xsvfInfo; - - xsvfInitialize( &xsvfInfo ); - - while ( !xsvfInfo.iErrorCode && (!xsvfInfo.ucComplete) ) - { - xsvfRun( &xsvfInfo ); - } - - if ( xsvfInfo.iErrorCode ) - { - XSVFDBG_PRINTF1( 0, "%s\n", xsvf_pzErrorName[ - ( xsvfInfo.iErrorCode < XSVF_ERROR_LAST ) - ? xsvfInfo.iErrorCode : XSVF_ERROR_UNKNOWN ] ); - XSVFDBG_PRINTF2( 0, "ERROR at or near XSVF command #%ld. See line #%ld in the XSVF ASCII file.\n", - xsvfInfo.lCommandCount, xsvfInfo.lCommandCount ); - } - else - { - XSVFDBG_PRINTF( 0, "SUCCESS - Completed XSVF execution.\n" ); - } - - xsvfCleanup( &xsvfInfo ); - - return( XSVF_ERRORCODE(xsvfInfo.iErrorCode) ); -} - - -/***************************************************************************** - * Function: do_cpld - * Description: main function. - * Specified here for creating stand-alone debug executable. - * Embedded users should call xsvfExecute() directly. - * Parameters: iArgc - number of command-line arguments. - * ppzArgv - array of ptrs to strings (command-line arguments). - * Returns: int - Legacy return value: 1 = success; 0 = error. - *****************************************************************************/ -int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int iErrorCode; - unsigned long duration; - unsigned long long startClock, endClock; - - if (argc == 2) - xsvfdata = (unsigned char *)simple_strtoul(argv[1], NULL, 16); - else { -#ifdef CONFIG_SYS_XSVF_DEFAULT_ADDR - xsvfdata = (unsigned char *)CONFIG_SYS_XSVF_DEFAULT_ADDR; -#else - printf("Usage:\ncpld %s\n", cmdtp->help); - return -1; -#endif - } - - iErrorCode = XSVF_ERRORCODE( XSVF_ERROR_NONE ); - xsvf_iDebugLevel = 0; - - printf("XSVF Player v%s, Xilinx, Inc.\n", XSVF_VERSION); - printf("Reading XSVF data @ %p\n", xsvfdata); - - /* Initialize the I/O. SetPort initializes I/O on first call */ - setPort( TMS, 1 ); - - /* Execute the XSVF in the file */ - startClock = get_ticks(); - iErrorCode = xsvfExecute(); - endClock = get_ticks(); - duration = (unsigned long)(endClock - startClock); - printf("\nExecution Time = %d seconds\n", (int)(duration/get_tbclk())); - - return( iErrorCode ); -} -U_BOOT_CMD( - cpld, 2, 1, do_cpld, - "program onboard CPLD", - "<xsvf-addr>" -); diff --git a/board/esd/common/xilinx_jtag/micro.h b/board/esd/common/xilinx_jtag/micro.h deleted file mode 100644 index e9a7612..0000000 --- a/board/esd/common/xilinx_jtag/micro.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * (C) Copyright 2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/***************************************************************************** - * File: micro.h - * Description: This header file contains the function prototype to the - * primary interface function for the XSVF player. - * Usage: FIRST - PORTS.C - * Customize the ports.c function implementations to establish - * the correct protocol for communicating with your JTAG ports - * (setPort() and readTDOBit()) and tune the waitTime() delay - * function. Also, establish access to the XSVF data source - * in the readByte() function. - * FINALLY - Call xsvfExecute(). - *****************************************************************************/ -#ifndef XSVF_MICRO_H -#define XSVF_MICRO_H - -/* Legacy error codes for xsvfExecute from original XSVF player v2.0 */ -#define XSVF_LEGACY_SUCCESS 1 -#define XSVF_LEGACY_ERROR 0 - -/* 4.04 [NEW] Error codes for xsvfExecute. */ -/* Must #define XSVF_SUPPORT_ERRORCODES in micro.c to get these codes */ -#define XSVF_ERROR_NONE 0 -#define XSVF_ERROR_UNKNOWN 1 -#define XSVF_ERROR_TDOMISMATCH 2 -#define XSVF_ERROR_MAXRETRIES 3 /* TDO mismatch after max retries */ -#define XSVF_ERROR_ILLEGALCMD 4 -#define XSVF_ERROR_ILLEGALSTATE 5 -#define XSVF_ERROR_DATAOVERFLOW 6 /* Data > lenVal MAX_LEN buffer size*/ -/* Insert new errors here */ -#define XSVF_ERROR_LAST 7 - -/***************************************************************************** - * Function: xsvfExecute - * Description: Process, interpret, and apply the XSVF commands. - * See port.c:readByte for source of XSVF data. - * Parameters: none. - * Returns: int - For error codes see above. - *****************************************************************************/ -int xsvfExecute(void); - -#endif /* XSVF_MICRO_H */ diff --git a/board/esd/common/xilinx_jtag/ports.c b/board/esd/common/xilinx_jtag/ports.c deleted file mode 100644 index d79dbd1..0000000 --- a/board/esd/common/xilinx_jtag/ports.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * (C) Copyright 2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/*******************************************************/ -/* file: ports.c */ -/* abstract: This file contains the routines to */ -/* output values on the JTAG ports, to read */ -/* the TDO bit, and to read a byte of data */ -/* from the prom */ -/* */ -/*******************************************************/ - -#include <common.h> -#include <asm/processor.h> -#include <asm/io.h> - -#include "ports.h" - -static unsigned long output = 0; -static int filepos = 0; -static int oldstate = 0; -static int newstate = 0; -static int readptr = 0; - -extern const unsigned char *xsvfdata; - -/* if in debugging mode, then just set the variables */ -void setPort(short p,short val) -{ - if (p==TMS) { - if (val) { - output |= JTAG_TMS; - } else { - output &= ~JTAG_TMS; - } - } - if (p==TDI) { - if (val) { - output |= JTAG_TDI; - } else { - output &= ~JTAG_TDI; - } - } - if (p==TCK) { - if (val) { - output |= JTAG_TCK; - } else { - output &= ~JTAG_TCK; - } - out_be32((void *)GPIO0_OR, output); - } -} - - -/* toggle tck LH */ -void pulseClock(void) -{ - setPort(TCK,0); /* set the TCK port to low */ - setPort(TCK,1); /* set the TCK port to high */ -} - - -/* read in a byte of data from the prom */ -void readByte(unsigned char *data) -{ - /* pretend reading using a file */ - *data = xsvfdata[readptr++]; - newstate = filepos++ >> 10; - if (newstate != oldstate) { - printf("%4d kB\r\r\r\r", newstate); - oldstate = newstate; - } -} - -/* read the TDO bit from port */ -unsigned char readTDOBit(void) -{ - unsigned long inputs; - - inputs = in_be32((void *)GPIO0_IR); - if (inputs & JTAG_TDO) - return 1; - else - return 0; -} - - -/* Wait at least the specified number of microsec. */ -/* Use a timer if possible; otherwise estimate the number of instructions */ -/* necessary to be run based on the microcontroller speed. For this example */ -/* we pulse the TCK port a number of times based on the processor speed. */ -void waitTime(long microsec) -{ - udelay(microsec); /* esd */ -} diff --git a/board/esd/common/xilinx_jtag/ports.h b/board/esd/common/xilinx_jtag/ports.h deleted file mode 100644 index 8ee7de9..0000000 --- a/board/esd/common/xilinx_jtag/ports.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * (C) Copyright 2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/*******************************************************/ -/* file: ports.h */ -/* abstract: This file contains extern declarations */ -/* for providing stimulus to the JTAG ports.*/ -/*******************************************************/ - -#ifndef ports_dot_h -#define ports_dot_h - -/* these constants are used to send the appropriate ports to setPort */ -/* they should be enumerated types, but some of the microcontroller */ -/* compilers don't like enumerated types */ -#define TCK (short) 0 -#define TMS (short) 1 -#define TDI (short) 2 - -/* - * Use CONFIG_SYS_FPGA_xxx defines from board include file. - */ -#define JTAG_TMS CONFIG_SYS_FPGA_PRG /* output */ -#define JTAG_TCK CONFIG_SYS_FPGA_CLK /* output */ -#define JTAG_TDI CONFIG_SYS_FPGA_DATA /* output */ -#define JTAG_TDO CONFIG_SYS_FPGA_DONE /* input */ - -/* set the port "p" (TCK, TMS, or TDI) to val (0 or 1) */ -void setPort(short p, short val); - -/* read the TDO bit and store it in val */ -unsigned char readTDOBit(void); - -/* make clock go down->up->down*/ -void pulseClock(void); - -/* read the next byte of data from the xsvf file */ -void readByte(unsigned char *data); - -void waitTime(long microsec); - -#endif diff --git a/board/esd/cpci2dp/Kconfig b/board/esd/cpci2dp/Kconfig deleted file mode 100644 index 646e8ff..0000000 --- a/board/esd/cpci2dp/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_CPCI2DP - -config SYS_BOARD - default "cpci2dp" - -config SYS_VENDOR - default "esd" - -config SYS_CONFIG_NAME - default "CPCI2DP" - -endif diff --git a/board/esd/cpci2dp/MAINTAINERS b/board/esd/cpci2dp/MAINTAINERS deleted file mode 100644 index 660e185..0000000 --- a/board/esd/cpci2dp/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -CPCI2DP BOARD -M: Matthias Fuchs <matthias.fuchs@esd-electronics.com> -S: Maintained -F: board/esd/cpci2dp/ -F: include/configs/CPCI2DP.h -F: configs/CPCI2DP_defconfig diff --git a/board/esd/cpci2dp/Makefile b/board/esd/cpci2dp/Makefile deleted file mode 100644 index ce2c6dd..0000000 --- a/board/esd/cpci2dp/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = cpci2dp.o flash.o ../common/misc.o ../common/cmd_loadpci.o diff --git a/board/esd/cpci2dp/cpci2dp.c b/board/esd/cpci2dp/cpci2dp.c deleted file mode 100644 index 336c551..0000000 --- a/board/esd/cpci2dp/cpci2dp.c +++ /dev/null @@ -1,172 +0,0 @@ -/* - * (C) Copyright 2005 - * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <command.h> -#include <malloc.h> - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f (void) -{ - unsigned long CPC0_CR0Reg; - - /* - * Setup GPIO pins - */ - CPC0_CR0Reg = mfdcr(CPC0_CR0); - mtdcr(CPC0_CR0, CPC0_CR0Reg | - ((CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED | - CONFIG_SYS_SELF_RST | CONFIG_SYS_INTA_FAKE) << 5)); - - /* set output pins to high */ - out_be32((void *)GPIO0_OR, CONFIG_SYS_EEPROM_WP); - /* setup for output (LED=off) */ - out_be32((void *)GPIO0_TCR, CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED); - - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) PB0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) PB1; active low; level sensitive - * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive - * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive - * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive - * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive - * IRQ 31 (EXT IRQ 6) unused - */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ - mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */ - - mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - return 0; -} - -int misc_init_r (void) -{ - unsigned long CPC0_CR0Reg; - - /* adjust flash start and offset */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; - gd->bd->bi_flashoffset = 0; - - /* - * Select cts (and not dsr) on uart1 - */ - CPC0_CR0Reg = mfdcr(CPC0_CR0); - mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000); - - return (0); -} - - -/* - * Check Board Identity: - */ -int checkboard (void) -{ - char str[64]; - int i = getenv_f("serial#", str, sizeof(str)); - - puts ("Board: "); - - if (i == -1) { - puts ("### No HW ID - assuming CPCI2DP"); - } else { - puts(str); - } - - printf(" (Ver 1.0)"); - - putc ('\n'); - - return 0; -} - -#if defined(CONFIG_SYS_EEPROM_WREN) -/* Input: <dev_addr> I2C address of EEPROM device to enable. - * <state> -1: deliver current state - * 0: disable write - * 1: enable write - * Returns: -1: wrong device address - * 0: dis-/en- able done - * 0/1: current state if <state> was -1. - */ -int eeprom_write_enable (unsigned dev_addr, int state) { - if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) { - return -1; - } else { - switch (state) { - case 1: - /* Enable write access, clear bit GPIO_SINT2. */ - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP); - state = 0; - break; - case 0: - /* Disable write access, set bit GPIO_SINT2. */ - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP); - state = 0; - break; - default: - /* Read current status back. */ - state = (0 == (in_be32((void *)GPIO0_OR) & - CONFIG_SYS_EEPROM_WP)); - break; - } - } - return state; -} -#endif - -#if defined(CONFIG_SYS_EEPROM_WREN) -int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int query = argc == 1; - int state = 0; - - if (query) { - /* Query write access state. */ - state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1); - if (state < 0) { - puts ("Query of write access state failed.\n"); - } else { - printf ("Write access for device 0x%0x is %sabled.\n", - CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis"); - state = 0; - } - } else { - if ('0' == argv[1][0]) { - /* Disable write access. */ - state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0); - } else { - /* Enable write access. */ - state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1); - } - if (state < 0) { - puts ("Setup of write access state failed.\n"); - } - } - - return state; -} - -U_BOOT_CMD( - eepwren, 2, 0, do_eep_wren, - "Enable / disable / query EEPROM write access", - "" -); -#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ diff --git a/board/esd/cpci2dp/flash.c b/board/esd/cpci2dp/flash.c deleted file mode 100644 index 34bdc05..0000000 --- a/board/esd/cpci2dp/flash.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - uint pbcr; - unsigned long base_b0; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0<<20); - } - - /* Setup offsets */ - flash_get_offsets (-size_b0, &flash_info[0]); - - /* Re-do sizing to get full correct info */ - mtdcr(EBC0_CFGADDR, PB0CR); - pbcr = mfdcr(EBC0_CFGDATA); - mtdcr(EBC0_CFGADDR, PB0CR); - base_b0 = -size_b0; - pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17); - mtdcr(EBC0_CFGDATA, pbcr); - /* printf("PB1CR = %x\n", pbcr); */ - - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - -monitor_flash_len, - 0xffffffff, - &flash_info[0]); - - flash_info[0].size = size_b0; - - return (size_b0); -} diff --git a/board/esd/cpci405/Kconfig b/board/esd/cpci405/Kconfig deleted file mode 100644 index 0df2755..0000000 --- a/board/esd/cpci405/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_CPCI4052 - -config SYS_BOARD - default "cpci405" - -config SYS_VENDOR - default "esd" - -config SYS_CONFIG_NAME - default "CPCI4052" - -endif diff --git a/board/esd/cpci405/MAINTAINERS b/board/esd/cpci405/MAINTAINERS deleted file mode 100644 index 1da58dc..0000000 --- a/board/esd/cpci405/MAINTAINERS +++ /dev/null @@ -1,12 +0,0 @@ -CPCI405 BOARD -M: Matthias Fuchs <matthias.fuchs@esd-electronics.com> -S: Maintained -F: board/esd/cpci405/ -F: include/configs/CPCI405.h -F: configs/CPCI405_defconfig -F: include/configs/CPCI4052.h -F: configs/CPCI4052_defconfig -F: include/configs/CPCI405AB.h -F: configs/CPCI405AB_defconfig -F: include/configs/CPCI405DT.h -F: configs/CPCI405DT_defconfig diff --git a/board/esd/cpci405/Makefile b/board/esd/cpci405/Makefile deleted file mode 100644 index 7490b78..0000000 --- a/board/esd/cpci405/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = cpci405.o flash.o ../common/misc.o -obj-y += ../common/cmd_loadpci.o diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c deleted file mode 100644 index c510ab1..0000000 --- a/board/esd/cpci405/cpci405.c +++ /dev/null @@ -1,496 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> -#include <console.h> -#include <libfdt.h> -#include <fdt_support.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <command.h> -#include <malloc.h> -#include <net.h> -#include <pci.h> - -DECLARE_GLOBAL_DATA_PTR; - -extern void __ft_board_setup(void *blob, bd_t *bd); - -#undef FPGA_DEBUG - -/* fpga configuration data - generated by bin2cc */ -const unsigned char fpgadata[] = -{ -#if defined(CONFIG_CPCI405_VER2) -# include "fpgadata_cpci4052.c" -#endif -}; - -/* - * include common fpga code (for esd boards) - */ -#include "../common/fpga.c" - -/* Prototypes */ -int cpci405_version(void); -void lxt971_no_sleep(void); - -int board_early_init_f(void) -{ -#ifndef CONFIG_CPCI405_VER2 - int index, len, i; - int status; -#endif - -#ifdef FPGA_DEBUG - /* set up serial port with default baudrate */ - (void)get_clocks(); - gd->baudrate = CONFIG_BAUDRATE; - serial_init(); - console_init_f(); -#endif - - /* - * First pull fpga-prg pin low, - * to disable fpga logic (on version 2 board) - */ - out_be32((void *)GPIO0_ODR, 0x00000000); /* no open drain pins */ - out_be32((void *)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */ - out_be32((void *)GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */ - out_be32((void *)GPIO0_OR, 0); /* pull prg low */ - - /* - * Boot onboard FPGA - */ -#ifndef CONFIG_CPCI405_VER2 - if (cpci405_version() == 1) { - status = fpga_boot((unsigned char *)fpgadata, sizeof(fpgadata)); - if (status != 0) { - /* booting FPGA failed */ -#ifndef FPGA_DEBUG - /* set up serial port with default baudrate */ - (void)get_clocks(); - gd->baudrate = CONFIG_BAUDRATE; - serial_init(); - console_init_f(); -#endif - printf("\nFPGA: Booting failed "); - switch (status) { - case ERROR_FPGA_PRG_INIT_LOW: - printf("(Timeout: INIT not low after " - "asserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_INIT_HIGH: - printf("(Timeout: INIT not high after " - "deasserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_DONE: - printf("(Timeout: DONE not high after " - "programming FPGA)\n "); - break; - } - - /* display infos on fpgaimage */ - index = 15; - for (i = 0; i < 4; i++) { - len = fpgadata[index]; - printf("FPGA: %s\n", &(fpgadata[index + 1])); - index += len + 3; - } - putc('\n'); - /* delayed reboot */ - for (i = 20; i > 0; i--) { - printf("Rebooting in %2d seconds \r",i); - for (index = 0; index < 1000; index++) - udelay(1000); - } - putc('\n'); - do_reset(NULL, 0, 0, NULL); - } - } -#endif /* !CONFIG_CPCI405_VER2 */ - - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052); active low; level sens. - * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive - * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive - * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive - * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive - */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ -#if defined(CONFIG_CPCI405_6U) - if (cpci405_version() == 3) { - mtdcr(UIC0PR, 0xFFFFFF99); /* set int polarities */ - } else { - mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */ - } -#else - mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */ -#endif - mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr(UIC0VCR, 0x00000001); /* set vect base=0, - * INT0 highest priority */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - return 0; -} - -int ctermm2(void) -{ -#if defined(CONFIG_CPCI405_VER2) - return 0; /* no, board is cpci405 */ -#else - if ((in_8((void*)0xf0000400) == 0x00) && - (in_8((void*)0xf0000401) == 0x01)) - return 0; /* no, board is cpci405 */ - else - return -1; /* yes, board is cterm-m2 */ -#endif -} - -int cpci405_host(void) -{ - if (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN) - return -1; /* yes, board is cpci405 host */ - else - return 0; /* no, board is cpci405 adapter */ -} - -int cpci405_version(void) -{ - unsigned long CPC0_CR0Reg; - unsigned long value; - - /* - * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO) - */ - CPC0_CR0Reg = mfdcr(CPC0_CR0); - mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03000000); - out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000); - out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000); - udelay(1000); /* wait some time before reading input */ - value = in_be32((void*)GPIO0_IR) & 0x00180000; /* get config bits */ - - /* - * Restore GPIO settings - */ - mtdcr(CPC0_CR0, CPC0_CR0Reg); - - switch (value) { - case 0x00180000: - /* CS2==1 && CS3==1 -> version 1 */ - return 1; - case 0x00080000: - /* CS2==0 && CS3==1 -> version 2 */ - return 2; - case 0x00100000: - /* CS2==1 && CS3==0 -> version 3 or 6U board */ - return 3; - case 0x00000000: - /* CS2==0 && CS3==0 -> version 4 */ - return 4; - default: - /* should not be reached! */ - return 2; - } -} - -int misc_init_r (void) -{ - unsigned long CPC0_CR0Reg; - - /* adjust flash start and offset */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; - gd->bd->bi_flashoffset = 0; - -#if defined(CONFIG_CPCI405_VER2) - { - unsigned char *dst; - ulong len = sizeof(fpgadata); - int status; - int index; - int i; - - /* - * On CPCI-405 version 2 the environment is saved in eeprom! - * FPGA can be gzip compressed (malloc) and booted this late. - */ - if (cpci405_version() >= 2) { - /* - * Setup GPIO pins (CS6+CS7 as GPIO) - */ - CPC0_CR0Reg = mfdcr(CPC0_CR0); - mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000); - - dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); - if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, - (uchar *)fpgadata, &len) != 0) { - printf("GUNZIP ERROR - must RESET board to recover\n"); - do_reset(NULL, 0, 0, NULL); - } - - status = fpga_boot(dst, len); - if (status != 0) { - printf("\nFPGA: Booting failed "); - switch (status) { - case ERROR_FPGA_PRG_INIT_LOW: - printf("(Timeout: INIT not low after " - "asserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_INIT_HIGH: - printf("(Timeout: INIT not high after " - "deasserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_DONE: - printf("(Timeout: DONE not high after " - "programming FPGA)\n "); - break; - } - - /* display infos on fpgaimage */ - index = 15; - for (i = 0; i < 4; i++) { - len = dst[index]; - printf("FPGA: %s\n", &(dst[index + 1])); - index += len + 3; - } - putc('\n'); - /* delayed reboot */ - for (i = 20; i > 0; i--) { - printf("Rebooting in %2d seconds \r", i); - for (index = 0; index < 1000; index++) - udelay(1000); - } - putc('\n'); - do_reset(NULL, 0, 0, NULL); - } - - /* restore gpio/cs settings */ - mtdcr(CPC0_CR0, CPC0_CR0Reg); - - puts("FPGA: "); - - /* display infos on fpgaimage */ - index = 15; - for (i = 0; i < 4; i++) { - len = dst[index]; - printf("%s ", &(dst[index + 1])); - index += len + 3; - } - putc('\n'); - - free(dst); - - /* - * Reset FPGA via FPGA_DATA pin - */ - SET_FPGA(FPGA_PRG | FPGA_CLK); - udelay(1000); /* wait 1ms */ - SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); - udelay(1000); /* wait 1ms */ - -#if defined(CONFIG_CPCI405_6U) -#error HIER GETH ES WEITER MIT IO ACCESSORS - if (cpci405_version() == 3) { - /* - * Enable outputs in fpga on version 3 board - */ - out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR, - in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) | - CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT); - - /* - * Set outputs to 0 - */ - out_8((void*)CONFIG_SYS_LED_ADDR, 0x00); - - /* - * Reset external DUART - */ - out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR, - in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) | - CONFIG_SYS_FPGA_MODE_DUART_RESET); - udelay(100); - out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR, - in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) & - ~CONFIG_SYS_FPGA_MODE_DUART_RESET); - } -#endif - } - else { - puts("\n*** U-Boot Version does not match Board Version!\n"); - puts("*** CPCI-405 Version 1.x detected!\n"); - puts("*** Please use correct U-Boot version " - "(CPCI405 instead of CPCI4052)!\n\n"); - } - } -#else /* CONFIG_CPCI405_VER2 */ - if (cpci405_version() >= 2) { - puts("\n*** U-Boot Version does not match Board Version!\n"); - puts("*** CPCI-405 Board Version 2.x detected!\n"); - puts("*** Please use correct U-Boot version " - "(CPCI4052 instead of CPCI405)!\n\n"); - } -#endif /* CONFIG_CPCI405_VER2 */ - - /* - * Select cts (and not dsr) on uart1 - */ - CPC0_CR0Reg = mfdcr(CPC0_CR0); - mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000); - - return 0; -} - -/* - * Check Board Identity: - */ - -int checkboard(void) -{ -#ifndef CONFIG_CPCI405_VER2 - int index; - int len; -#endif - char str[64]; - int i = getenv_f("serial#", str, sizeof(str)); - unsigned short ver; - - puts("Board: "); - - if (i == -1) - puts("### No HW ID - assuming CPCI405"); - else - puts(str); - - ver = cpci405_version(); - printf(" (Ver %d.x, ", ver); - - if (ctermm2()) { - char str[4]; - - /* - * Read board-id and save in env-variable - */ - sprintf(str, "%d", *(unsigned char *)0xf0000400); - setenv("boardid", str); - printf("CTERM-M2 - Id=%s)", str); - } else { - if (cpci405_host()) - puts("PCI Host Version)"); - else - puts("PCI Adapter Version)"); - } - -#ifndef CONFIG_CPCI405_VER2 - puts("\nFPGA: "); - - /* display infos on fpgaimage */ - index = 15; - for (i = 0; i < 4; i++) { - len = fpgadata[index]; - printf("%s ", &(fpgadata[index + 1])); - index += len + 3; - } -#endif - - putc('\n'); - return 0; -} - -void reset_phy(void) -{ -#if defined(CONFIG_LXT971_NO_SLEEP) - - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); -#endif -} - -#if defined(CONFIG_CPCI405_VER2) && defined (CONFIG_IDE_RESET) -void ide_set_reset(int on) -{ - /* - * Assert or deassert CompactFlash Reset Pin - */ - if (on) { /* assert RESET */ - out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR, - in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) & - ~CONFIG_SYS_FPGA_MODE_CF_RESET); - } else { /* release RESET */ - out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR, - in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) | - CONFIG_SYS_FPGA_MODE_CF_RESET); - } -} - -#endif /* CONFIG_IDE_RESET && CONFIG_CPCI405_VER2 */ - -#if defined(CONFIG_PCI) -void cpci405_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) -{ - unsigned char int_line = 0xff; - - /* - * Write pci interrupt line register (cpci405 specific) - */ - switch (PCI_DEV(dev) & 0x03) { - case 0: - int_line = 27 + 2; - break; - case 1: - int_line = 27 + 3; - break; - case 2: - int_line = 27 + 0; - break; - case 3: - int_line = 27 + 1; - break; - } - - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line); -} - -int pci_pre_init(struct pci_controller *hose) -{ - hose->fixup_irq = cpci405_pci_fixup_irq; - return 1; -} -#endif /* defined(CONFIG_PCI) */ - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, bd_t *bd) -{ - int rc; - - __ft_board_setup(blob, bd); - - /* - * Disable PCI in adapter mode. - */ - if (!cpci405_host()) { - rc = fdt_find_and_setprop(blob, "/plb/pci@ec000000", "status", - "disabled", sizeof("disabled"), 1); - if (rc) { - printf("Unable to update property status in PCI node, " - "err=%s\n", - fdt_strerror(rc)); - } - } - - return 0; -} -#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/esd/cpci405/flash.c b/board/esd/cpci405/flash.c deleted file mode 100644 index 091652b..0000000 --- a/board/esd/cpci405/flash.c +++ /dev/null @@ -1,138 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long calc_size(unsigned long size) -{ - switch (size) { - case 1 << 20: - return 0; - case 2 << 20: - return 1; - case 4 << 20: - return 2; - case 8 << 20: - return 3; - case 16 << 20: - return 4; - default: - return 0; - } -} - - -unsigned long flash_init (void) -{ - unsigned long size_b0, size_b1; - int i; - uint pbcr; - unsigned long base_b0, base_b1; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - base_b0 = FLASH_BASE0_PRELIM; - size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0 << 20); - } - - base_b1 = FLASH_BASE1_PRELIM; - size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]); - - /* Re-do sizing to get full correct info */ - - if (size_b1) { - if (size_b1 < (1 << 20)) { - /* minimum CS size on PPC405GP is 1MB !!! */ - size_b1 = 1 << 20; - } - base_b1 = -size_b1; - mtdcr (EBC0_CFGADDR, PB0CR); - pbcr = mfdcr (EBC0_CFGDATA); - mtdcr (EBC0_CFGADDR, PB0CR); - pbcr = (pbcr & 0x0001ffff) | base_b1 | (calc_size(size_b1) << 17); - mtdcr (EBC0_CFGDATA, pbcr); -#if 0 /* test-only */ - printf("size_b1=%x base_b1=%x PB1CR = %x\n", - size_b1, base_b1, pbcr); /* test-only */ -#endif - } - - if (size_b0) { - if (size_b0 < (1 << 20)) { - /* minimum CS size on PPC405GP is 1MB !!! */ - size_b0 = 1 << 20; - } - base_b0 = base_b1 - size_b0; - mtdcr (EBC0_CFGADDR, PB1CR); - pbcr = mfdcr (EBC0_CFGDATA); - mtdcr (EBC0_CFGADDR, PB1CR); - pbcr = (pbcr & 0x0001ffff) | base_b0 | (calc_size(size_b0) << 17); - mtdcr (EBC0_CFGDATA, pbcr); -#if 0 /* test-only */ - printf("size_b0=%x base_b0=%x PB0CR = %x\n", - size_b0, base_b0, pbcr); /* test-only */ -#endif - } - - size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]); - - flash_get_offsets (base_b0, &flash_info[0]); - - /* monitor protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - base_b0 + size_b0 - monitor_flash_len, - base_b0 + size_b0 - 1, &flash_info[0]); - - if (size_b1) { - /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]); - - flash_get_offsets (base_b1, &flash_info[1]); - - /* monitor protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - base_b1 + size_b1 - monitor_flash_len, - base_b1 + size_b1 - 1, &flash_info[1]); - /* monitor protection OFF by default (one is enough) */ - flash_protect (FLAG_PROTECT_CLEAR, - base_b0 + size_b0 - monitor_flash_len, - base_b0 + size_b0 - 1, &flash_info[0]); - } else { - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - } - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - - return (size_b0 + size_b1); -} diff --git a/board/esd/cpci405/fpgadata_cpci4052.c b/board/esd/cpci405/fpgadata_cpci4052.c deleted file mode 100644 index bedbb1f..0000000 --- a/board/esd/cpci405/fpgadata_cpci4052.c +++ /dev/null @@ -1,1529 +0,0 @@ -0x1f, 0x8b, 0x08, 0x08, 0xe9, 0xf4, 0x75, 0x3e, -0x00, 0x03, 0x63, 0x70, 0x63, 0x69, 0x34, 0x30, -0x35, 0x5f, 0x32, 0x5f, 0x30, 0x34, 0x2e, 0x62, -0x69, 0x74, 0x00, 0xed, 0x7c, 0x0f, 0x74, 0x14, -0xd7, 0x79, 0xef, 0x37, 0x77, 0x66, 0xc5, 0x68, -0x77, 0xa5, 0x1d, 0xad, 0x56, 0xce, 0xda, 0x16, -0xf2, 0x68, 0x25, 0xc8, 0xa2, 0xae, 0xc4, 0xb2, -0xc2, 0x58, 0x96, 0xc5, 0x6a, 0xb4, 0x92, 0xe9, -0xda, 0xe0, 0xb0, 0x26, 0x6e, 0xc3, 0x6b, 0xfd, -0x92, 0xc5, 0x26, 0xad, 0xfa, 0x0e, 0x71, 0x85, -0xd3, 0xe6, 0xa9, 0x6e, 0x5f, 0xdf, 0xd5, 0x6a, -0x31, 0x02, 0x61, 0x58, 0xff, 0x69, 0xa3, 0xb8, -0x24, 0x59, 0x88, 0xda, 0x28, 0x2e, 0xc9, 0x5b, -0x04, 0x01, 0x61, 0x1c, 0x7b, 0x50, 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configs/PLU405_defconfig diff --git a/board/esd/plu405/Makefile b/board/esd/plu405/Makefile deleted file mode 100644 index 6ffae67..0000000 --- a/board/esd/plu405/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = plu405.o flash.o \ - ../common/misc.o \ - ../common/esd405ep_nand.o \ diff --git a/board/esd/plu405/flash.c b/board/esd/plu405/flash.c deleted file mode 100644 index 23e8164..0000000 --- a/board/esd/plu405/flash.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - uint pbcr; - unsigned long base_b0; - int size_val = 0; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0<<20); - } - - /* Setup offsets */ - flash_get_offsets (-size_b0, &flash_info[0]); - - /* Re-do sizing to get full correct info */ - mtdcr(EBC0_CFGADDR, PB0CR); - pbcr = mfdcr(EBC0_CFGDATA); - mtdcr(EBC0_CFGADDR, PB0CR); - base_b0 = -size_b0; - switch (size_b0) { - case 1 << 20: - size_val = 0; - break; - case 2 << 20: - size_val = 1; - break; - case 4 << 20: - size_val = 2; - break; - case 8 << 20: - size_val = 3; - break; - case 16 << 20: - size_val = 4; - break; - } - pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); - mtdcr(EBC0_CFGDATA, pbcr); - - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - -CONFIG_SYS_MONITOR_LEN, - 0xffffffff, - &flash_info[0]); - - flash_info[0].size = size_b0; - - return (size_b0); -} diff --git a/board/esd/plu405/fpgadata.c b/board/esd/plu405/fpgadata.c deleted file mode 100644 index 485b9a2..0000000 --- a/board/esd/plu405/fpgadata.c +++ /dev/null @@ -1,2358 +0,0 @@ -0x1f, 0x8b, 0x08, 0x08, 0x04, 0x44, 0x9f, 0x46, -0x00, 0x03, 0x70, 0x6c, 0x75, 0x34, 0x30, 0x35, -0x5f, 0x31, 0x5f, 0x31, 0x2e, 0x62, 0x69, 0x74, -0x00, 0x94, 0x9a, 0x0f, 0x70, 0x14, 0x55, 0x9e, -0xc7, 0x7f, 0xfd, 0xba, 0x93, 0x74, 0xa6, 0x3b, -0xe9, 0x36, 0x7f, 0x30, 0xb7, 0x08, 0xd7, 0x19, -0x07, 0x76, 0xc4, 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compressed and generated by bin2c */ -const unsigned char fpgadata[] = -{ -#include "fpgadata.c" -}; - -/* - * include common fpga code (for esd boards) - */ -#include "../common/fpga.c" - -/* - * generate a short spike on the CAN tx line - * to bring the couplers in sync - */ -void init_coupler(u32 addr) -{ - struct sja1000_basic_s *ctrl = (struct sja1000_basic_s *)addr; - - /* reset */ - out_8(&ctrl->cr, CR_RR); - - /* dominant */ - out_8(&ctrl->btr0, 0x00); /* btr setup is required */ - out_8(&ctrl->btr1, 0x14); /* we use 1Mbit/s */ - out_8(&ctrl->oc, OC_TP1 | OC_TN1 | OC_POL1 | - OC_TP0 | OC_TN0 | OC_POL0 | OC_MODE1); - out_8(&ctrl->cr, 0x00); - - /* delay */ - in_8(&ctrl->cr); - in_8(&ctrl->cr); - in_8(&ctrl->cr); - in_8(&ctrl->cr); - - /* reset */ - out_8(&ctrl->cr, CR_RR); -} - -int board_early_init_f(void) -{ - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive - * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive - * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive - * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive - * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive - */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ - mtdcr(UIC0PR, 0xFFFFFF99); /* set int polarities */ - mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest prio */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - /* - * EBC Configuration Register: set ready timeout to - * 512 ebc-clks -> ca. 15 us - */ - mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */ - - return 0; -} - -int misc_init_r(void) -{ - unsigned char *dst; - unsigned char fctr; - ulong len = sizeof(fpgadata); - int status; - int index; - int i; - - /* adjust flash start and offset */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; - gd->bd->bi_flashoffset = 0; - - dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); - if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, - (uchar *)fpgadata, &len) != 0) { - printf("GUNZIP ERROR - must RESET board to recover\n"); - do_reset(NULL, 0, 0, NULL); - } - - status = fpga_boot(dst, len); - if (status != 0) { - printf("\nFPGA: Booting failed "); - switch (status) { - case ERROR_FPGA_PRG_INIT_LOW: - printf("(Timeout: INIT not low " - "after asserting PROGRAM*)\n"); - break; - case ERROR_FPGA_PRG_INIT_HIGH: - printf("(Timeout: INIT not high " - "after deasserting PROGRAM*)\n"); - break; - case ERROR_FPGA_PRG_DONE: - printf("(Timeout: DONE not high " - "after programming FPGA)\n"); - break; - } - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("FPGA: %s\n", &(dst[index+1])); - index += len+3; - } - putc ('\n'); - /* delayed reboot */ - for (i=20; i>0; i--) { - printf("Rebooting in %2d seconds \r",i); - for (index=0;index<1000;index++) - udelay(1000); - } - putc('\n'); - do_reset(NULL, 0, 0, NULL); - } - - puts("FPGA: "); - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("%s ", &(dst[index+1])); - index += len+3; - } - putc('\n'); - - free(dst); - - /* - * Reset FPGA via FPGA_DATA pin - */ - SET_FPGA(FPGA_PRG | FPGA_CLK); - udelay(1000); /* wait 1ms */ - SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); - udelay(1000); /* wait 1ms */ - - /* - * Reset external DUARTs - */ - out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) | CONFIG_SYS_DUART_RST); - udelay(10); - out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_DUART_RST); - udelay(1000); - - /* - * Set NAND-FLASH GPIO signals to default - */ - out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) & - ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE)); - out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) | CONFIG_SYS_NAND_CE); - - /* - * Setup EEPROM write protection - */ - out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP); - out_be32((void*)GPIO0_TCR, - in_be32((void*)GPIO0_TCR) | CONFIG_SYS_EEPROM_WP); - - /* - * Enable interrupts in exar duart mcr[3] - */ - out_8((void *)DUART0_BA + 4, 0x08); - out_8((void *)DUART1_BA + 4, 0x08); - - /* - * Enable auto RS485 mode in 2nd external uart - */ - out_8((void *)DUART1_BA + 3, 0xbf); /* write LCR */ - fctr = in_8((void *)DUART1_BA + 1); /* read FCTR */ - fctr |= 0x08; /* enable RS485 mode */ - out_8((void *)DUART1_BA + 1, fctr); /* write FCTR */ - out_8((void *)DUART1_BA + 3, 0); /* write LCR */ - - /* - * Init magnetic couplers - */ - if (!getenv("noinitcoupler")) { - init_coupler(CAN0_BA); - init_coupler(CAN1_BA); - } - return 0; -} - -/* - * Check Board Identity: - */ -int checkboard(void) -{ - char str[64]; - int i = getenv_f("serial#", str, sizeof(str)); - - puts("Board: "); - - if (i == -1) - puts("### No HW ID - assuming PLU405"); - else - puts(str); - - putc('\n'); - return 0; -} - -#ifdef CONFIG_IDE_RESET -#define FPGA_CTRL (CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL) -void ide_set_reset(int on) -{ - /* - * Assert or deassert CompactFlash Reset Pin - */ - if (on) { /* assert RESET */ - out_be16((void *)FPGA_CTRL, - in_be16((void *)FPGA_CTRL) & - ~CONFIG_SYS_FPGA_CTRL_CF_RESET); - } else { /* release RESET */ - out_be16((void *)FPGA_CTRL, - in_be16((void *)FPGA_CTRL) | - CONFIG_SYS_FPGA_CTRL_CF_RESET); - } -} -#endif /* CONFIG_IDE_RESET */ - -void reset_phy(void) -{ -#ifdef CONFIG_LXT971_NO_SLEEP - - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); -#endif -} - -#if defined(CONFIG_SYS_EEPROM_WREN) -/* Input: <dev_addr> I2C address of EEPROM device to enable. - * <state> -1: deliver current state - * 0: disable write - * 1: enable write - * Returns: -1: wrong device address - * 0: dis-/en- able done - * 0/1: current state if <state> was -1. - */ -int eeprom_write_enable(unsigned dev_addr, int state) -{ - if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) { - return -1; - } else { - switch (state) { - case 1: - /* Enable write access, clear bit GPIO0. */ - out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) & - ~CONFIG_SYS_EEPROM_WP); - state = 0; - break; - case 0: - /* Disable write access, set bit GPIO0. */ - out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) | - CONFIG_SYS_EEPROM_WP); - state = 0; - break; - default: - /* Read current status back. */ - state = ((in_be32((void*)GPIO0_OR) & - CONFIG_SYS_EEPROM_WP) == 0); - break; - } - } - return state; -} - -int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int query = argc == 1; - int state = 0; - - if (query) { - /* Query write access state. */ - state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1); - if (state < 0) { - puts("Query of write access state failed.\n"); - } else { - printf("Write access for device 0x%0x is %sabled.\n", - CONFIG_SYS_I2C_EEPROM_ADDR, - state ? "en" : "dis"); - state = 0; - } - } else { - if (argv[1][0] == '0') { - /* Disable write access. */ - state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, - 0); - } else { - /* Enable write access. */ - state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, - 1); - } - if (state < 0) - puts("Setup of write access state failed.\n"); - } - - return state; -} - -U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, - "Enable / disable / query EEPROM write access", - "" -); -#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ diff --git a/board/esd/pmc405de/Kconfig b/board/esd/pmc405de/Kconfig deleted file mode 100644 index 4b05787..0000000 --- a/board/esd/pmc405de/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_PMC405DE - -config SYS_BOARD - default "pmc405de" - -config SYS_VENDOR - default "esd" - -config SYS_CONFIG_NAME - default "PMC405DE" - -endif diff --git a/board/esd/pmc405de/MAINTAINERS b/board/esd/pmc405de/MAINTAINERS deleted file mode 100644 index a891e23..0000000 --- a/board/esd/pmc405de/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -PMC405DE BOARD -M: Matthias Fuchs <matthias.fuchs@esd-electronics.com> -S: Maintained -F: board/esd/pmc405de/ -F: include/configs/PMC405DE.h -F: configs/PMC405DE_defconfig diff --git a/board/esd/pmc405de/Makefile b/board/esd/pmc405de/Makefile deleted file mode 100644 index b3f6dcd..0000000 --- a/board/esd/pmc405de/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = pmc405de.o -obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o -obj-y += ../common/cmd_loadpci.o diff --git a/board/esd/pmc405de/chip_config.c b/board/esd/pmc405de/chip_config.c deleted file mode 100644 index c06a6ae..0000000 --- a/board/esd/pmc405de/chip_config.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * (C) Copyright 2008-2009 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx_config.h> - -struct ppc4xx_config ppc4xx_config_val[] = { - { - "133", - "CPU: 133 PLB: 133 OPB: 66 EBC: 44 PCI: 44/66", - { - 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x40, 0x12, 0x12, 0x42, 0x3e, 0x00, 0x00 - } - }, - { - "266", - "CPU: 266 PLB: 133 OPB: 66 EBC: 44 PCI: 44/66", - { - 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x50, 0x22, 0x2d, 0x42, 0x3e, 0x00, 0x00 - } - }, - { - "333", - "CPU: 333 PLB: 111 OPB: 55 EBC: 55 PCI: 55/111", - { - 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x60, 0x29, 0x2d, 0x42, 0xbe, 0x00, 0x00 - } - }, -}; - -int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val); diff --git a/board/esd/pmc405de/pmc405de.c b/board/esd/pmc405de/pmc405de.c deleted file mode 100644 index 31ac728..0000000 --- a/board/esd/pmc405de/pmc405de.c +++ /dev/null @@ -1,507 +0,0 @@ -/* - * (C) Copyright 2009 - * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd.eu - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <console.h> -#include <libfdt.h> -#include <fdt_support.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/ppc4xx-gpio.h> -#include <asm/4xx_pci.h> -#include <command.h> -#include <malloc.h> - -/* - * PMC405-DE cpld registers - * - all registers are 8 bit - * - all registers are on 32 bit addesses - */ -struct pmc405de_cpld { - /* cpld design version */ - u8 version; - u8 reserved0[3]; - - /* misc. status lines */ - u8 status; - u8 reserved1[3]; - - /* - * gated control flags - * gate bit(s) must be written with '1' to - * access control flag - */ - u8 control; - u8 reserved2[3]; -}; - -#define CPLD_VERSION_MASK 0x0f -#define CPLD_CONTROL_POSTLED_N 0x01 -#define CPLD_CONTROL_POSTLED_GATE 0x02 -#define CPLD_CONTROL_RESETOUT_N 0x40 -#define CPLD_CONTROL_RESETOUT_N_GATE 0x80 - -DECLARE_GLOBAL_DATA_PTR; - -extern void __ft_board_setup(void *blob, bd_t *bd); -extern void pll_write(u32 a, u32 b); - -static int wait_for_pci_ready_done; - -static int is_monarch(void); -static int pci_is_66mhz(void); -static int board_revision(void); -static int cpld_revision(void); -static void upd_plb_pci_div(u32 pllmr0, u32 pllmr1, u32 div); - -int board_early_init_f(void) -{ - u32 pllmr0, pllmr1; - - /* - * check M66EN and patch PLB:PCI divider for 66MHz PCI - * - * fCPU==333MHz && fPCI==66MHz (PLBDiv==3 && M66EN==1): PLB/PCI=1 - * fCPU==333MHz && fPCI==33MHz (PLBDiv==3 && M66EN==0): PLB/PCI=2 - * fCPU==133|266MHz && fPCI==66MHz (PLBDiv==1|2 && M66EN==1): PLB/PCI=2 - * fCPU==133|266MHz && fPCI==33MHz (PLBDiv==1|2 && M66EN==0): PLB/PCI=3 - * - * calling upd_plb_pci_div() may end in calling pll_write() which will - * do a chip reset and never return. - */ - pllmr0 = mfdcr(CPC0_PLLMR0); - pllmr1 = mfdcr(CPC0_PLLMR1); - - if ((pllmr0 & PLLMR0_CPU_TO_PLB_MASK) == PLLMR0_CPU_PLB_DIV_3) { - /* fCPU=333MHz, fPLB=111MHz */ - if (pci_is_66mhz()) - upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_1); - else - upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_2); - } else { - /* fCPU=133|266MHz, fPLB=133MHz */ - if (pci_is_66mhz()) - upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_2); - else - upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_3); - } - - /* - * IRQ 25 (EXT IRQ 0) PCI-INTA#; active low; level sensitive - * IRQ 26 (EXT IRQ 1) PCI-INTB#; active low; level sensitive - * IRQ 27 (EXT IRQ 2) PCI-INTC#; active low; level sensitive - * IRQ 28 (EXT IRQ 3) PCI-INTD#; active low; level sensitive - * IRQ 29 (EXT IRQ 4) ETH0-PHY-IRQ#; active low; level sensitive - * IRQ 30 (EXT IRQ 5) ETH1-PHY-IRQ#; active low; level sensitive - * IRQ 31 (EXT IRQ 6) PLD-IRQ#; active low; level sensitive - */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ - mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */ - mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr(UIC0VCR, 0x00000001); /* set vect base=0, INT0 highest prio */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - /* - * EBC Configuration Register: - * - set ready timeout to 512 ebc-clks -> ca. 15 us - * - EBC lines are always driven - */ - mtebc(EBC0_CFG, 0xa8400000); - - return 0; -} - -static void upd_plb_pci_div(u32 pllmr0, u32 pllmr1, u32 div) -{ - if ((pllmr0 & PLLMR0_PCI_TO_PLB_MASK) != div) - pll_write((pllmr0 & ~PLLMR0_PCI_TO_PLB_MASK) | div, pllmr1); -} - -int misc_init_r(void) -{ - int i; - struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE; - struct pmc405de_cpld *cpld = - (struct pmc405de_cpld *)CONFIG_SYS_CPLD_BASE; - - if (!is_monarch()) { - /* PCI configuration done: release EREADY */ - setbits_be32(&gpio0->or, CONFIG_SYS_GPIO_EREADY); - setbits_be32(&gpio0->tcr, CONFIG_SYS_GPIO_EREADY); - } - - /* turn off POST LED */ - out_8(&cpld->control, - CPLD_CONTROL_POSTLED_N | CPLD_CONTROL_POSTLED_GATE); - - /* turn on LEDs: RUN, A, B */ - clrbits_be32(&gpio0->or, - CONFIG_SYS_GPIO_LEDRUN_N | - CONFIG_SYS_GPIO_LEDA_N | - CONFIG_SYS_GPIO_LEDB_N); - - for (i=0; i < 200; i++) - udelay(1000); - - /* turn off LEDs: A, B */ - setbits_be32(&gpio0->or, - CONFIG_SYS_GPIO_LEDA_N | - CONFIG_SYS_GPIO_LEDB_N); - - return (0); -} - -static int is_monarch(void) -{ - struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE; - return (in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_MONARCH_N) == 0; -} - -static int pci_is_66mhz(void) -{ - struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE; - return (in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_M66EN); -} - -static int board_revision(void) -{ - struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE; - return ((in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_HWREV_MASK) >> - CONFIG_SYS_GPIO_HWREV_SHIFT); -} - -static int cpld_revision(void) -{ - struct pmc405de_cpld *cpld = - (struct pmc405de_cpld *)CONFIG_SYS_CPLD_BASE; - return ((in_8(&cpld->version) & CPLD_VERSION_MASK)); -} - -/* - * Check Board Identity - */ -int checkboard(void) -{ - puts("Board: esd GmbH - PMC-CPU/405-DE"); - - gd->board_type = board_revision(); - printf(", Rev 1.%ld, ", gd->board_type); - - if (!is_monarch()) - puts("non-"); - - printf("monarch, PCI=%s MHz, PLD-Rev 1.%d\n", - pci_is_66mhz() ? "66" : "33", cpld_revision()); - - return 0; -} - - -static void wait_for_pci_ready(void) -{ - struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE; - int i; - char *s = getenv("pcidelay"); - - /* only wait once */ - if (wait_for_pci_ready_done) - return; - - /* - * We have our own handling of the pcidelay variable. - * Using CONFIG_PCI_BOOTDELAY enables pausing for host - * and adapter devices. For adapter devices we do not - * want this. - */ - if (s) { - int ms = simple_strtoul(s, NULL, 10); - printf("PCI: Waiting for %d ms\n", ms); - for (i=0; i<ms; i++) - udelay(1000); - } - - if (!(in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_EREADY)) { - printf("PCI: Waiting for EREADY (CTRL-C to skip) ... "); - while (1) { - if (ctrlc()) { - puts("abort\n"); - break; - } - if (in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_EREADY) { - printf("done\n"); - break; - } - } - } - - wait_for_pci_ready_done = 1; -} - -/* - * Overwrite weak is_pci_host() - * - * This routine is called to determine if a pci scan should be - * performed. With various hardware environments (especially cPCI and - * PPMC) it's insufficient to depend on the state of the arbiter enable - * bit in the strap register, or generic host/adapter assumptions. - * - * Return 0 for adapter mode, non-zero for host (monarch) mode. - */ -int is_pci_host(struct pci_controller *hose) -{ - char *s; - - if (!is_monarch()) { - /* - * Overwrite PCI identification when running in - * non-monarch mode - * This should be moved into pci_target_init() - * when it is sometimes available for 405 CPUs - */ - pci_write_config_word(PCIDEVID_405GP, - PCI_SUBSYSTEM_ID, - CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH); - pci_write_config_word(PCIDEVID_405GP, - PCI_CLASS_SUB_CODE, - CONFIG_SYS_PCI_CLASSCODE_NONMONARCH); - } - - s = getenv("pciscan"); - if (s == NULL) { - if (is_monarch()) { - wait_for_pci_ready(); - return 1; - } else { - return 0; - } - } else { - if (!strcmp(s, "yes")) - return 1; - } - - return 0; -} - -/* - * Overwrite weak pci_pre_init() - * - * The default implementation enables the 405EP - * internal PCI arbiter. We do not want that - * on a PMC module. - */ -int pci_pre_init(struct pci_controller *hose) -{ - return 1; -} - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, bd_t *bd) -{ - int rc; - - __ft_board_setup(blob, bd); - - /* - * Disable PCI in non-monarch mode. - */ - if (!is_monarch()) { - rc = fdt_find_and_setprop(blob, "/plb/pci@ec000000", "status", - "disabled", sizeof("disabled"), 1); - if (rc) { - printf("Unable to update property status in PCI node, " - "err=%s\n", - fdt_strerror(rc)); - } - } - - return 0; -} -#endif /* CONFIG_OF_BOARD_SETUP */ - -#if defined(CONFIG_SYS_EEPROM_WREN) -/* Input: <dev_addr> I2C address of EEPROM device to enable. - * <state> -1: deliver current state - * 0: disable write - * 1: enable write - * Returns: -1: wrong device address - * 0: dis-/en- able done - * 0/1: current state if <state> was -1. - */ -int eeprom_write_enable(unsigned dev_addr, int state) -{ - struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE; - - if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) { - return -1; - } else { - switch (state) { - case 1: - /* Enable write access, clear bit GPIO0. */ - clrbits_be32(&gpio0->or, CONFIG_SYS_GPIO_EEPROM_WP); - state = 0; - break; - case 0: - /* Disable write access, set bit GPIO0. */ - setbits_be32(&gpio0->or, CONFIG_SYS_GPIO_EEPROM_WP); - state = 0; - break; - default: - /* Read current status back. */ - state = (0 == (in_be32(&gpio0->or) & - CONFIG_SYS_GPIO_EEPROM_WP)); - break; - } - } - return state; -} - -int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int query = argc == 1; - int state = 0; - - if (query) { - /* Query write access state. */ - state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, - 1); - if (state < 0) { - puts("Query of write access state failed.\n"); - } else { - printf("Write access for device 0x%0x is %sabled.\n", - CONFIG_SYS_I2C_EEPROM_ADDR, - state ? "en" : "dis"); - state = 0; - } - } else { - if ('0' == argv[1][0]) { - /* Disable write access. */ - state = eeprom_write_enable( - CONFIG_SYS_I2C_EEPROM_ADDR, 0); - } else { - /* Enable write access. */ - state = eeprom_write_enable( - CONFIG_SYS_I2C_EEPROM_ADDR, 1); - } - if (state < 0) - puts ("Setup of write access state failed.\n"); - } - - return state; -} - -U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, - "Enable / disable / query EEPROM write access", - "" -); -#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ - -#if defined(CONFIG_PRAM) -#include <environment.h> - -int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - u32 pram, nextbase, base; - char *v; - u32 param; - ulong *lptr; - - v = getenv("pram"); - if (v) - pram = simple_strtoul(v, NULL, 10); - else { - printf("Error: pram undefined. Please define pram in KiB\n"); - return 1; - } - - base = gd->bd->bi_memsize; -#if defined(CONFIG_LOGBUFFER) - base -= LOGBUFF_LEN + LOGBUFF_OVERHEAD; -#endif - /* - * gd->bd->bi_memsize == physical ram size - CONFIG_SYS_MM_TOP_HIDE - */ - param = base - (pram << 10); - printf("PARAM: @%08x\n", param); - debug("memsize=0x%08x, base=0x%08x\n", (u32)gd->bd->bi_memsize, base); - - /* clear entire PA ram */ - memset((void*)param, 0, (pram << 10)); - - /* reserve 4k for pointer field */ - nextbase = base - 4096; - lptr = (ulong*)(base); - - /* - * *(--lptr) = item_size; - * *(--lptr) = base - item_base = distance from field top; - */ - - /* env is first (4k aligned) */ - nextbase -= ((CONFIG_ENV_SIZE + 4096 - 1) & ~(4096 - 1)); - memcpy((void*)nextbase, env_ptr, CONFIG_ENV_SIZE); - *(--lptr) = CONFIG_ENV_SIZE; /* size */ - *(--lptr) = base - nextbase; /* offset | type=0 */ - - /* free section */ - *(--lptr) = nextbase - param; /* size */ - *(--lptr) = (base - param) | 126; /* offset | type=126 */ - - /* terminate pointer field */ - *(--lptr) = crc32(0, (void*)(base - 0x10), 0x10); - *(--lptr) = 0; /* offset=0 -> terminator */ - return 0; -} -U_BOOT_CMD( - painit, 1, 1, do_painit, - "prepare PciAccess system", - "" -); -#endif /* CONFIG_PRAM */ - -int do_selfreset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE; - setbits_be32(&gpio0->tcr, CONFIG_SYS_GPIO_SELFRST_N); - return 0; -} -U_BOOT_CMD( - selfreset, 1, 1, do_selfreset, - "assert self-reset# signal", - "" -); - -int do_resetout(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - struct pmc405de_cpld *cpld = - (struct pmc405de_cpld *)CONFIG_SYS_CPLD_BASE; - - if (argc > 1) { - if (argv[1][0] == '0') { - /* assert */ - printf("PMC-RESETOUT# asserted\n"); - out_8(&cpld->control, - CPLD_CONTROL_RESETOUT_N_GATE); - } else { - /* deassert */ - printf("PMC-RESETOUT# deasserted\n"); - out_8(&cpld->control, - CPLD_CONTROL_RESETOUT_N | - CPLD_CONTROL_RESETOUT_N_GATE); - } - } else { - printf("PMC-RESETOUT# is %s\n", - (in_8(&cpld->control) & CPLD_CONTROL_RESETOUT_N) ? - "inactive" : "active"); - } - return 0; -} -U_BOOT_CMD( - resetout, 2, 1, do_resetout, - "assert PMC-RESETOUT# signal", - "" -); diff --git a/board/esd/pmc440/Kconfig b/board/esd/pmc440/Kconfig deleted file mode 100644 index df8bd65..0000000 --- a/board/esd/pmc440/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_PMC440 - -config SYS_BOARD - default "pmc440" - -config SYS_VENDOR - default "esd" - -config SYS_CONFIG_NAME - default "PMC440" - -endif diff --git a/board/esd/pmc440/MAINTAINERS b/board/esd/pmc440/MAINTAINERS deleted file mode 100644 index 32fb9ba..0000000 --- a/board/esd/pmc440/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -PMC440 BOARD -M: Matthias Fuchs <matthias.fuchs@esd-electronics.com> -S: Maintained -F: board/esd/pmc440/ -F: include/configs/PMC440.h -F: configs/PMC440_defconfig diff --git a/board/esd/pmc440/Makefile b/board/esd/pmc440/Makefile deleted file mode 100644 index 708e9d1..0000000 --- a/board/esd/pmc440/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2002-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = pmc440.o cmd_pmc440.o sdram.o fpga.o \ - ../common/cmd_loadpci.o -extra-y += init.o diff --git a/board/esd/pmc440/cmd_pmc440.c b/board/esd/pmc440/cmd_pmc440.c deleted file mode 100644 index b7cd595..0000000 --- a/board/esd/pmc440/cmd_pmc440.c +++ /dev/null @@ -1,554 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Matthias Fuchs, esd Gmbh, matthias.fuchs@esd-electronics.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> -#include <command.h> -#include <console.h> -#include <asm/io.h> -#include <asm/cache.h> -#include <asm/processor.h> -#if defined(CONFIG_LOGBUFFER) -#include <logbuff.h> -#endif - -#include "pmc440.h" - -int is_monarch(void); -int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset, - uchar *buffer, unsigned cnt); -int eeprom_write_enable(unsigned dev_addr, int state); - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_CMD_BSP) - -static int got_fifoirq; -static int got_hcirq; - -int fpga_interrupt(u32 arg) -{ - pmc440_fpga_t *fpga = (pmc440_fpga_t *)arg; - int rc = -1; /* not for us */ - u32 status = FPGA_IN32(&fpga->status); - - /* check for interrupt from fifo module */ - if (status & STATUS_FIFO_ISF) { - /* disable this int source */ - FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_FIFOIE_GATE); - rc = 0; - got_fifoirq = 1; /* trigger backend */ - } - - if (status & STATUS_HOST_ISF) { - FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_HCINT_GATE); - rc = 0; - got_hcirq = 1; - } - - return rc; -} - -int do_waithci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA; - - got_hcirq = 0; - - FPGA_CLRBITS(&fpga->ctrla, CTRL_HOST_IE); - FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_HCINT_GATE); - - irq_install_handler(IRQ0_FPGA, - (interrupt_handler_t *)fpga_interrupt, - fpga); - - FPGA_SETBITS(&fpga->ctrla, CTRL_HOST_IE); - - while (!got_hcirq) { - /* Abort if ctrl-c was pressed */ - if (ctrlc()) { - puts("\nAbort\n"); - break; - } - } - if (got_hcirq) - printf("Got interrupt!\n"); - - FPGA_CLRBITS(&fpga->ctrla, CTRL_HOST_IE); - irq_free_handler(IRQ0_FPGA); - return 0; -} -U_BOOT_CMD( - waithci, 1, 1, do_waithci, - "Wait for host control interrupt", - "" -); - -void dump_fifo(pmc440_fpga_t *fpga, int f, int *n) -{ - u32 ctrl; - - while (!((ctrl = FPGA_IN32(&fpga->fifo[f].ctrl)) & FIFO_EMPTY)) { - printf("%5d %d %3d %08x", - (*n)++, f, ctrl & (FIFO_LEVEL_MASK | FIFO_FULL), - FPGA_IN32(&fpga->fifo[f].data)); - if (ctrl & FIFO_OVERFLOW) { - printf(" OVERFLOW\n"); - FPGA_CLRBITS(&fpga->fifo[f].ctrl, FIFO_OVERFLOW); - } else - printf("\n"); - } -} - -int do_fifo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA; - int i; - int n = 0; - u32 ctrl, data, f; - char str[] = "\\|/-"; - int abort = 0; - int count = 0; - int count2 = 0; - - switch (argc) { - case 1: - /* print all fifos status information */ - printf("fifo level status\n"); - printf("______________________________\n"); - for (i=0; i<FIFO_COUNT; i++) { - ctrl = FPGA_IN32(&fpga->fifo[i].ctrl); - printf(" %d %3d %s%s%s %s\n", - i, ctrl & (FIFO_LEVEL_MASK | FIFO_FULL), - ctrl & FIFO_FULL ? "FULL " : "", - ctrl & FIFO_EMPTY ? "EMPTY " : "", - ctrl & (FIFO_FULL|FIFO_EMPTY) ? "" : "NOT EMPTY", - ctrl & FIFO_OVERFLOW ? "OVERFLOW" : ""); - } - break; - - case 2: - /* completely read out fifo 'n' */ - if (!strcmp(argv[1],"read")) { - printf(" # fifo level data\n"); - printf("______________________________\n"); - - for (i=0; i<FIFO_COUNT; i++) - dump_fifo(fpga, i, &n); - - } else if (!strcmp(argv[1],"wait")) { - got_fifoirq = 0; - - irq_install_handler(IRQ0_FPGA, - (interrupt_handler_t *)fpga_interrupt, - fpga); - - printf(" # fifo level data\n"); - printf("______________________________\n"); - - /* enable all fifo interrupts */ - FPGA_OUT32(&fpga->hostctrl, - HOSTCTRL_FIFOIE_GATE | HOSTCTRL_FIFOIE_FLAG); - for (i=0; i<FIFO_COUNT; i++) { - /* enable interrupts from all fifos */ - FPGA_SETBITS(&fpga->fifo[i].ctrl, FIFO_IE); - } - - while (1) { - /* wait loop */ - while (!got_fifoirq) { - count++; - if (!(count % 100)) { - count2++; - putc(0x08); /* backspace */ - putc(str[count2 % 4]); - } - - /* Abort if ctrl-c was pressed */ - if ((abort = ctrlc())) { - puts("\nAbort\n"); - break; - } - udelay(1000); - } - if (abort) - break; - - /* simple fifo backend */ - if (got_fifoirq) { - for (i=0; i<FIFO_COUNT; i++) - dump_fifo(fpga, i, &n); - - got_fifoirq = 0; - /* unmask global fifo irq */ - FPGA_OUT32(&fpga->hostctrl, - HOSTCTRL_FIFOIE_GATE | - HOSTCTRL_FIFOIE_FLAG); - } - } - - /* disable all fifo interrupts */ - FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_FIFOIE_GATE); - for (i=0; i<FIFO_COUNT; i++) - FPGA_CLRBITS(&fpga->fifo[i].ctrl, FIFO_IE); - - irq_free_handler(IRQ0_FPGA); - - } else { - printf("Usage:\nfifo %s\n", cmdtp->help); - return 1; - } - break; - - case 4: - case 5: - if (!strcmp(argv[1],"write")) { - /* get fifo number or fifo address */ - f = simple_strtoul(argv[2], NULL, 16); - - /* data paramter */ - data = simple_strtoul(argv[3], NULL, 16); - - /* get optional count parameter */ - n = 1; - if (argc >= 5) - n = (int)simple_strtoul(argv[4], NULL, 10); - - if (f < FIFO_COUNT) { - printf("writing %d x %08x to fifo %d\n", - n, data, f); - for (i=0; i<n; i++) - FPGA_OUT32(&fpga->fifo[f].data, data); - } else { - printf("writing %d x %08x to fifo port at " - "address %08x\n", - n, data, f); - for (i=0; i<n; i++) - out_be32((void *)f, data); - } - } else { - printf("Usage:\nfifo %s\n", cmdtp->help); - return 1; - } - break; - - default: - printf("Usage:\nfifo %s\n", cmdtp->help); - return 1; - } - return 0; -} -U_BOOT_CMD( - fifo, 5, 1, do_fifo, - "Fifo module operations", - "wait\nfifo read\n" - "fifo write fifo(0..3) data [cnt=1]\n" - "fifo write address(>=4) data [cnt=1]\n" - " - without arguments: print all fifo's status\n" - " - with 'wait' argument: interrupt driven read from all fifos\n" - " - with 'read' argument: read current contents from all fifos\n" - " - with 'write' argument: write 'data' 'cnt' times to " - "'fifo' or 'address'" -); - -int do_setup_bootstrap_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - ulong sdsdp[5]; - ulong delay; - int count=16; - - if (argc < 2) { - printf("Usage:\nsbe %s\n", cmdtp->help); - return -1; - } - - if (argc > 1) { - if (!strcmp(argv[1], "400")) { - /* PLB=133MHz, PLB/PCI=3 */ - printf("Bootstrapping for 400MHz\n"); - sdsdp[0]=0x8678624e; - sdsdp[1]=0x095fa030; - sdsdp[2]=0x40082350; - sdsdp[3]=0x0d050000; - } else if (!strcmp(argv[1], "533")) { - /* PLB=133MHz, PLB/PCI=3 */ - printf("Bootstrapping for 533MHz\n"); - sdsdp[0]=0x87788252; - sdsdp[1]=0x095fa030; - sdsdp[2]=0x40082350; - sdsdp[3]=0x0d050000; - } else if (!strcmp(argv[1], "667")) { - /* PLB=133MHz, PLB/PCI=3 */ - printf("Bootstrapping for 667MHz\n"); - sdsdp[0]=0x8778a256; - sdsdp[1]=0x095fa030; - sdsdp[2]=0x40082350; - sdsdp[3]=0x0d050000; - } else { - printf("Usage:\nsbe %s\n", cmdtp->help); - return -1; - } - } - - if (argc > 2) { - sdsdp[4] = 0; - if (argv[2][0]=='1') - sdsdp[4]=0x19750100; - else if (argv[2][0]=='0') - sdsdp[4]=0x19750000; - if (sdsdp[4]) - count += 4; - } - - if (argc > 3) { - delay = simple_strtoul(argv[3], NULL, 10); - if (delay > 20) - delay = 20; - sdsdp[4] |= delay; - } - - printf("Writing boot EEPROM ...\n"); - if (bootstrap_eeprom_write(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR, - 0, (uchar*)sdsdp, count) != 0) - printf("bootstrap_eeprom_write failed\n"); - else - printf("done (dump via 'i2c md 52 0.1 14')\n"); - - return 0; -} -U_BOOT_CMD( - sbe, 4, 0, do_setup_bootstrap_eeprom, - "setup bootstrap eeprom", - "<cpufreq:400|533|667> [<console-uart:0|1> [<bringup delay (0..20s)>]]" -); - -#if defined(CONFIG_PRAM) -#include <environment.h> -#include <search.h> -#include <errno.h> - -int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - u32 pram, nextbase, base; - char *v; - u32 param; - ulong *lptr; - - env_t *envp; - char *res; - int len; - - v = getenv("pram"); - if (v) - pram = simple_strtoul(v, NULL, 10); - else { - printf("Error: pram undefined. Please define pram in KiB\n"); - return 1; - } - - base = (u32)gd->ram_size; -#if defined(CONFIG_LOGBUFFER) - base -= LOGBUFF_LEN + LOGBUFF_OVERHEAD; -#endif - /* - * gd->ram_size == physical ram size - CONFIG_SYS_MEM_TOP_HIDE - */ - param = base - (pram << 10); - printf("PARAM: @%08x\n", param); - debug("memsize=0x%08x, base=0x%08x\n", (u32)gd->ram_size, base); - - /* clear entire PA ram */ - memset((void*)param, 0, (pram << 10)); - - /* reserve 4k for pointer field */ - nextbase = base - 4096; - lptr = (ulong*)(base); - - /* - * *(--lptr) = item_size; - * *(--lptr) = base - item_base = distance from field top; - */ - - /* env is first (4k aligned) */ - nextbase -= ((CONFIG_ENV_SIZE + 4096 - 1) & ~(4096 - 1)); - envp = (env_t *)nextbase; - res = (char *)envp->data; - len = hexport_r(&env_htab, '\0', 0, &res, ENV_SIZE, 0, NULL); - if (len < 0) { - error("Cannot export environment: errno = %d\n", errno); - return 1; - } - envp->crc = crc32(0, envp->data, ENV_SIZE); - - *(--lptr) = CONFIG_ENV_SIZE; /* size */ - *(--lptr) = base - nextbase; /* offset | type=0 */ - - /* free section */ - *(--lptr) = nextbase - param; /* size */ - *(--lptr) = (base - param) | 126; /* offset | type=126 */ - - /* terminate pointer field */ - *(--lptr) = crc32(0, (void*)(base - 0x10), 0x10); - *(--lptr) = 0; /* offset=0 -> terminator */ - return 0; -} -U_BOOT_CMD( - painit, 1, 1, do_painit, - "prepare PciAccess system", - "" -); -#endif /* CONFIG_PRAM */ - -int do_selfreset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - in_be32((void*)CONFIG_SYS_RESET_BASE); - return 0; -} -U_BOOT_CMD( - selfreset, 1, 1, do_selfreset, - "assert self-reset# signal", - "" -); - -int do_resetout(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA; - - /* requiers bootet FPGA and PLD_IOEN_N active */ - if (in_be32((void*)GPIO1_OR) & GPIO1_IOEN_N) { - printf("Error: resetout requires a bootet FPGA\n"); - return -1; - } - - if (argc > 1) { - if (argv[1][0] == '0') { - /* assert */ - printf("PMC-RESETOUT# asserted\n"); - FPGA_OUT32(&fpga->hostctrl, - HOSTCTRL_PMCRSTOUT_GATE); - } else { - /* deassert */ - printf("PMC-RESETOUT# deasserted\n"); - FPGA_OUT32(&fpga->hostctrl, - HOSTCTRL_PMCRSTOUT_GATE | - HOSTCTRL_PMCRSTOUT_FLAG); - } - } else { - printf("PMC-RESETOUT# is %s\n", - FPGA_IN32(&fpga->hostctrl) & HOSTCTRL_PMCRSTOUT_FLAG ? - "inactive" : "active"); - } - - return 0; -} -U_BOOT_CMD( - resetout, 2, 1, do_resetout, - "assert PMC-RESETOUT# signal", - "" -); - -int do_inta(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - if (is_monarch()) { - printf("This command is only supported in non-monarch mode\n"); - return -1; - } - - if (argc > 1) { - if (argv[1][0] == '0') { - /* assert */ - printf("inta# asserted\n"); - out_be32((void*)GPIO1_TCR, - in_be32((void*)GPIO1_TCR) | GPIO1_INTA_FAKE); - } else { - /* deassert */ - printf("inta# deasserted\n"); - out_be32((void*)GPIO1_TCR, - in_be32((void*)GPIO1_TCR) & ~GPIO1_INTA_FAKE); - } - } else { - printf("inta# is %s\n", - in_be32((void*)GPIO1_TCR) & GPIO1_INTA_FAKE ? - "active" : "inactive"); - } - return 0; -} -U_BOOT_CMD( - inta, 2, 1, do_inta, - "Assert/Deassert or query INTA# state in non-monarch mode", - "" -); - -/* test-only */ -int do_pmm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - ulong pciaddr; - - if (argc > 1) { - pciaddr = simple_strtoul(argv[1], NULL, 16); - - pciaddr &= 0xf0000000; - - /* map PCI address at 0xc0000000 in PLB space */ - - /* PMM1 Mask/Attribute - disabled b4 setting */ - out32r(PCIL0_PMM1MA, 0x00000000); - /* PMM1 Local Address */ - out32r(PCIL0_PMM1LA, 0xc0000000); - /* PMM1 PCI Low Address */ - out32r(PCIL0_PMM1PCILA, pciaddr); - /* PMM1 PCI High Address */ - out32r(PCIL0_PMM1PCIHA, 0x00000000); - /* 256MB + No prefetching, and enable region */ - out32r(PCIL0_PMM1MA, 0xf0000001); - } else { - printf("Usage:\npmm %s\n", cmdtp->help); - } - return 0; -} -U_BOOT_CMD( - pmm, 2, 1, do_pmm, - "Setup pmm[1] registers", - "<pciaddr> (pciaddr will be aligned to 256MB)" -); - -#if defined(CONFIG_SYS_EEPROM_WREN) -int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int query = argc == 1; - int state = 0; - - if (query) { - /* Query write access state. */ - state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1); - if (state < 0) { - puts("Query of write access state failed.\n"); - } else { - printf("Write access for device 0x%0x is %sabled.\n", - CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis"); - state = 0; - } - } else { - if ('0' == argv[1][0]) { - /* Disable write access. */ - state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 0); - } else { - /* Enable write access. */ - state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 1); - } - if (state < 0) { - puts("Setup of write access state failed.\n"); - } - } - - return state; -} -U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, - "Enable / disable / query EEPROM write access", - "" -); -#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ - -#endif /* CONFIG_CMD_BSP */ diff --git a/board/esd/pmc440/config.mk b/board/esd/pmc440/config.mk deleted file mode 100644 index 9cb071e..0000000 --- a/board/esd/pmc440/config.mk +++ /dev/null @@ -1,16 +0,0 @@ -# -# (C) Copyright 2002-2010 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/board/esd/pmc440/fpga.c b/board/esd/pmc440/fpga.c deleted file mode 100644 index f876da8..0000000 --- a/board/esd/pmc440/fpga.c +++ /dev/null @@ -1,446 +0,0 @@ -/* - * (C) Copyright 2007 - * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <spartan2.h> -#include <spartan3.h> -#include <command.h> -#include "fpga.h" -#include "pmc440.h" - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_FPGA) - -#define USE_SP_CODE - -#ifdef USE_SP_CODE -xilinx_spartan3_slave_parallel_fns pmc440_fpga_fns = { - fpga_pre_config_fn, - fpga_pgm_fn, - fpga_init_fn, - NULL, /* err */ - fpga_done_fn, - fpga_clk_fn, - fpga_cs_fn, - fpga_wr_fn, - NULL, /* rdata */ - fpga_wdata_fn, - fpga_busy_fn, - fpga_abort_fn, - fpga_post_config_fn, -}; -#else -xilinx_spartan3_slave_serial_fns pmc440_fpga_fns = { - fpga_pre_config_fn, - fpga_pgm_fn, - fpga_clk_fn, - fpga_init_fn, - fpga_done_fn, - fpga_wr_fn, - fpga_post_config_fn, -}; -#endif - -xilinx_spartan2_slave_serial_fns ngcc_fpga_fns = { - ngcc_fpga_pre_config_fn, - ngcc_fpga_pgm_fn, - ngcc_fpga_clk_fn, - ngcc_fpga_init_fn, - ngcc_fpga_done_fn, - ngcc_fpga_wr_fn, - ngcc_fpga_post_config_fn -}; - -xilinx_desc fpga[CONFIG_FPGA_COUNT] = { - XILINX_XC3S1200E_DESC( -#ifdef USE_SP_CODE - slave_parallel, -#else - slave_serial, -#endif - (void *)&pmc440_fpga_fns, - 0), - XILINX_XC2S200_DESC( - slave_serial, - (void *)&ngcc_fpga_fns, - 0) -}; - - -/* - * Set the active-low FPGA reset signal. - */ -void fpga_reset(int assert) -{ - debug("%s:%d: RESET ", __FUNCTION__, __LINE__); - if (assert) { - out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_DATA); - debug("asserted\n"); - } else { - out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_DATA); - debug("deasserted\n"); - } -} - - -/* - * Initialize the SelectMap interface. We assume that the mode and the - * initial state of all of the port pins have already been set! - */ -void fpga_serialslave_init(void) -{ - debug("%s:%d: Initialize serial slave interface\n", __FUNCTION__, - __LINE__); - fpga_pgm_fn(false, false, 0); /* make sure program pin is inactive */ -} - - -/* - * Set the FPGA's active-low SelectMap program line to the specified level - */ -int fpga_pgm_fn(int assert, int flush, int cookie) -{ - debug("%s:%d: FPGA PROGRAM ", - __FUNCTION__, __LINE__); - - if (assert) { - out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_PRG); - debug("asserted\n"); - } else { - out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_PRG); - debug("deasserted\n"); - } - return assert; -} - - -/* - * Test the state of the active-low FPGA INIT line. Return 1 on INIT - * asserted (low). - */ -int fpga_init_fn(int cookie) -{ - if (in_be32((void*)GPIO1_IR) & GPIO1_FPGA_INIT) - return 0; - else - return 1; -} - -#ifdef USE_SP_CODE -int fpga_abort_fn(int cookie) -{ - return 0; -} - - -int fpga_cs_fn(int assert_cs, int flush, int cookie) -{ - return assert_cs; -} - - -int fpga_busy_fn(int cookie) -{ - return 1; -} -#endif - - -/* - * Test the state of the active-high FPGA DONE pin - */ -int fpga_done_fn(int cookie) -{ - if (in_be32((void*)GPIO1_IR) & GPIO1_FPGA_DONE) - return 1; - else - return 0; -} - - -/* - * FPGA pre-configuration function. Just make sure that - * FPGA reset is asserted to keep the FPGA from starting up after - * configuration. - */ -int fpga_pre_config_fn(int cookie) -{ - debug("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__); - fpga_reset(true); - - /* release init# */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | GPIO0_FPGA_FORCEINIT); - /* disable PLD IOs */ - out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_IOEN_N); - return 0; -} - - -/* - * FPGA post configuration function. Blip the FPGA reset line and then see if - * the FPGA appears to be running. - */ -int fpga_post_config_fn(int cookie) -{ - pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA; - int rc=0; - char *s; - - debug("%s:%d: FPGA post configuration\n", __FUNCTION__, __LINE__); - - /* enable PLD0..7 pins */ - out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_IOEN_N); - - fpga_reset(true); - udelay (100); - fpga_reset(false); - udelay (100); - - FPGA_OUT32(&fpga->status, (gd->board_type << STATUS_HWREV_SHIFT) & STATUS_HWREV_MASK); - - /* NGCC/CANDES only: enable ledlink */ - if ((s = getenv("bd_type")) && - ((!strcmp(s, "ngcc")) || (!strcmp(s, "candes")))) - FPGA_SETBITS(&fpga->ctrla, 0x29f8c000); - - return rc; -} - - -int fpga_clk_fn(int assert_clk, int flush, int cookie) -{ - if (assert_clk) - out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_CLK); - else - out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_CLK); - - return assert_clk; -} - - -int fpga_wr_fn(int assert_write, int flush, int cookie) -{ - if (assert_write) - out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_DATA); - else - out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_DATA); - - return assert_write; -} - -#ifdef USE_SP_CODE -int fpga_wdata_fn(uchar data, int flush, int cookie) -{ - uchar val = data; - ulong or = in_be32((void*)GPIO1_OR); - int i = 7; - do { - /* Write data */ - if (val & 0x80) - or = (or & ~GPIO1_FPGA_CLK) | GPIO1_FPGA_DATA; - else - or = or & ~(GPIO1_FPGA_CLK | GPIO1_FPGA_DATA); - - out_be32((void*)GPIO1_OR, or); - - /* Assert the clock */ - or |= GPIO1_FPGA_CLK; - out_be32((void*)GPIO1_OR, or); - val <<= 1; - i --; - } while (i > 0); - - /* Write last data bit (the 8th clock comes from the sp_load() code */ - if (val & 0x80) - or = (or & ~GPIO1_FPGA_CLK) | GPIO1_FPGA_DATA; - else - or = or & ~(GPIO1_FPGA_CLK | GPIO1_FPGA_DATA); - - out_be32((void*)GPIO1_OR, or); - - return 0; -} -#endif - -#define NGCC_FPGA_PRG CLOCK_EN -#define NGCC_FPGA_DATA RESET_OUT -#define NGCC_FPGA_DONE CLOCK_IN -#define NGCC_FPGA_INIT IRIGB_R_IN -#define NGCC_FPGA_CLK CLOCK_OUT - -void ngcc_fpga_serialslave_init(void) -{ - debug("%s:%d: Initialize serial slave interface\n", - __FUNCTION__, __LINE__); - - /* make sure program pin is inactive */ - ngcc_fpga_pgm_fn(false, false, 0); -} - -/* - * Set the active-low FPGA reset signal. - */ -void ngcc_fpga_reset(int assert) -{ - debug("%s:%d: RESET ", __FUNCTION__, __LINE__); - - if (assert) { - FPGA_CLRBITS(NGCC_CTRL_BASE, NGCC_CTRL_FPGARST_N); - debug("asserted\n"); - } else { - FPGA_SETBITS(NGCC_CTRL_BASE, NGCC_CTRL_FPGARST_N); - debug("deasserted\n"); - } -} - - -/* - * Set the FPGA's active-low SelectMap program line to the specified level - */ -int ngcc_fpga_pgm_fn(int assert, int flush, int cookie) -{ - pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA; - - debug("%s:%d: FPGA PROGRAM ", __FUNCTION__, __LINE__); - - if (assert) { - FPGA_CLRBITS(&fpga->ctrla, NGCC_FPGA_PRG); - debug("asserted\n"); - } else { - FPGA_SETBITS(&fpga->ctrla, NGCC_FPGA_PRG); - debug("deasserted\n"); - } - - return assert; -} - - -/* - * Test the state of the active-low FPGA INIT line. Return 1 on INIT - * asserted (low). - */ -int ngcc_fpga_init_fn(int cookie) -{ - pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA; - - debug("%s:%d: INIT check... ", __FUNCTION__, __LINE__); - if (FPGA_IN32(&fpga->status) & NGCC_FPGA_INIT) { - debug("high\n"); - return 0; - } else { - debug("low\n"); - return 1; - } -} - - -/* - * Test the state of the active-high FPGA DONE pin - */ -int ngcc_fpga_done_fn(int cookie) -{ - pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA; - - debug("%s:%d: DONE check... ", __FUNCTION__, __LINE__); - if (FPGA_IN32(&fpga->status) & NGCC_FPGA_DONE) { - debug("DONE high\n"); - return 1; - } else { - debug("low\n"); - return 0; - } -} - - -/* - * FPGA pre-configuration function. - */ -int ngcc_fpga_pre_config_fn(int cookie) -{ - pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA; - debug("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__); - - ngcc_fpga_reset(true); - FPGA_CLRBITS(&fpga->ctrla, 0xfffffe00); - - ngcc_fpga_reset(true); - return 0; -} - - -/* - * FPGA post configuration function. Blip the FPGA reset line and then see if - * the FPGA appears to be running. - */ -int ngcc_fpga_post_config_fn(int cookie) -{ - pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA; - - debug("%s:%d: NGCC FPGA post configuration\n", __FUNCTION__, __LINE__); - - udelay (100); - ngcc_fpga_reset(false); - - FPGA_SETBITS(&fpga->ctrla, 0x29f8c000); - - return 0; -} - - -int ngcc_fpga_clk_fn(int assert_clk, int flush, int cookie) -{ - pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA; - - if (assert_clk) - FPGA_SETBITS(&fpga->ctrla, NGCC_FPGA_CLK); - else - FPGA_CLRBITS(&fpga->ctrla, NGCC_FPGA_CLK); - - return assert_clk; -} - - -int ngcc_fpga_wr_fn(int assert_write, int flush, int cookie) -{ - pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA; - - if (assert_write) - FPGA_SETBITS(&fpga->ctrla, NGCC_FPGA_DATA); - else - FPGA_CLRBITS(&fpga->ctrla, NGCC_FPGA_DATA); - - return assert_write; -} - - -/* - * Initialize the fpga. Return 1 on success, 0 on failure. - */ -int pmc440_init_fpga(void) -{ - char *s; - - debug("%s:%d: Initialize FPGA interface\n", - __FUNCTION__, __LINE__); - fpga_init(); - - fpga_serialslave_init (); - debug("%s:%d: Adding fpga 0\n", __FUNCTION__, __LINE__); - fpga_add (fpga_xilinx, &fpga[0]); - - /* NGCC only */ - if ((s = getenv("bd_type")) && !strcmp(s, "ngcc")) { - ngcc_fpga_serialslave_init (); - debug("%s:%d: Adding fpga 1\n", __FUNCTION__, __LINE__); - fpga_add (fpga_xilinx, &fpga[1]); - } - - return 0; -} -#endif /* CONFIG_FPGA */ diff --git a/board/esd/pmc440/fpga.h b/board/esd/pmc440/fpga.h deleted file mode 100644 index 3810788..0000000 --- a/board/esd/pmc440/fpga.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * (C) Copyright 2007 - * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -extern int pmc440_init_fpga(void); - -extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie); -extern int fpga_init_fn(int cookie); -extern int fpga_err_fn(int cookie); -extern int fpga_done_fn(int cookie); -extern int fpga_clk_fn(int assert_clk, int flush, int cookie); -extern int fpga_cs_fn(int assert_cs, int flush, int cookie); -extern int fpga_wr_fn(int assert_write, int flush, int cookie); -extern int fpga_wdata_fn (uchar data, int flush, int cookie); -extern int fpga_read_data_fn(unsigned char *data, int cookie); -extern int fpga_write_data_fn(unsigned char data, int flush, int cookie); -extern int fpga_busy_fn(int cookie); -extern int fpga_abort_fn(int cookie ); -extern int fpga_pre_config_fn(int cookie ); -extern int fpga_post_config_fn(int cookie ); - -extern int ngcc_fpga_pgm_fn(int assert_pgm, int flush, int cookie); -extern int ngcc_fpga_init_fn(int cookie); -extern int ngcc_fpga_done_fn(int cookie); -extern int ngcc_fpga_clk_fn(int assert_clk, int flush, int cookie); -extern int ngcc_fpga_wr_fn(int assert_write, int flush, int cookie); -extern int ngcc_fpga_pre_config_fn(int cookie ); -extern int ngcc_fpga_post_config_fn(int cookie ); diff --git a/board/esd/pmc440/init.S b/board/esd/pmc440/init.S deleted file mode 100644 index 1f26fad..0000000 --- a/board/esd/pmc440/init.S +++ /dev/null @@ -1,69 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm-offsets.h> -#include <ppc_asm.tmpl> -#include <asm/mmu.h> -#include <config.h> - -/* - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - */ - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - - /* - * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the - * speed up boot process. It is patched after relocation to enable SA_I - */ - tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G ) - - /* TLB entries for DDR2 SDRAM are generated dynamically */ - -#ifdef CONFIG_SYS_INIT_RAM_DCACHE - /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G ) -#endif - - /* TLB-entry for PCI Memory */ - tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG ) - - /* TLB-entries for EBC */ - /* PMC440 maps EBC to 0xef000000 which is handled by the peripheral - * tlb entry. - * This dummy entry is only for convinience in order not to modify the - * amount of entries. Currently OS/9 relies on this :-) - */ - tlbentry( 0xc0000000, SZ_256M, 0xc0000000, 1, AC_RWX | SA_IG ) - - /* TLB-entry for NAND */ - tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_RWX | SA_IG ) - - /* TLB-entry for Internal Registers & OCM */ - tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_RWX | SA_I ) - - /*TLB-entry PCI registers*/ - tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG ) - - /* TLB-entry for peripherals */ - tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG) - - /* TLB-entry PCI IO space */ - tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RWX | SA_IG) - - /* TODO: what about high IO space */ - tlbtab_end diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c deleted file mode 100644 index 0d43505..0000000 --- a/board/esd/pmc440/pmc440.c +++ /dev/null @@ -1,906 +0,0 @@ -/* - * (Cg) Copyright 2007-2008 - * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com. - * Based on board/amcc/sequoia/sequoia.c - * - * (C) Copyright 2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2006 - * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com - * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> -#include <console.h> -#include <libfdt.h> -#include <fdt_support.h> -#include <asm/ppc440.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/bitops.h> -#include <command.h> -#include <i2c.h> -#ifdef CONFIG_RESET_PHY_R -#include <miiphy.h> -#endif -#include <serial.h> -#include <asm/4xx_pci.h> -#include <usb.h> - -#include "fpga.h" -#include "pmc440.h" - -DECLARE_GLOBAL_DATA_PTR; - -extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; -extern void __ft_board_setup(void *blob, bd_t *bd); - -ulong flash_get_size(ulong base, int banknum); -static int pci_is_66mhz(void); -int is_monarch(void); -static int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset, - uchar *buffer, unsigned cnt); - -struct serial_device *default_serial_console(void) -{ - uchar buf[4]; - ulong delay; - int i; - ulong val; - - /* - * Use default console on P4 when strapping jumper - * is installed (bootstrap option != 'H'). - */ - mfsdr(SDR0_PINSTP, val); - if (((val & 0xf0000000) >> 29) != 7) - return &eserial2_device; - - ulong scratchreg = in_be32((void *)GPIO0_ISR3L); - if (!(scratchreg & 0x80)) { - /* mark scratchreg valid */ - scratchreg = (scratchreg & 0xffffff00) | 0x80; - - i2c_init_all(); - - i = bootstrap_eeprom_read(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR, - 0x10, buf, 4); - if ((i != -1) && (buf[0] == 0x19) && (buf[1] == 0x75)) { - scratchreg |= buf[2]; - - /* bringup delay for console */ - for (delay = 0; delay < (1000 * (ulong)buf[3]); delay++) - udelay(1000); - } else - scratchreg |= 0x01; - out_be32((void *)GPIO0_ISR3L, scratchreg); - } - - if (scratchreg & 0x01) - return &eserial2_device; - else - return &eserial1_device; -} - -int board_early_init_f(void) -{ - u32 sdr0_cust0; - u32 sdr0_pfc1, sdr0_pfc2; - u32 reg; - - /* general EBC configuration (disable EBC timeouts) */ - mtdcr(EBC0_CFGADDR, EBC0_CFG); - mtdcr(EBC0_CFGDATA, 0xf8400000); - - /* Setup the GPIO pins */ - out_be32((void *)GPIO0_OR, 0x40000102); - out_be32((void *)GPIO0_TCR, 0x4c90011f); - out_be32((void *)GPIO0_OSRL, 0x28051400); - out_be32((void *)GPIO0_OSRH, 0x55005000); - out_be32((void *)GPIO0_TSRL, 0x08051400); - out_be32((void *)GPIO0_TSRH, 0x55005000); - out_be32((void *)GPIO0_ISR1L, 0x54000000); - out_be32((void *)GPIO0_ISR1H, 0x00000000); - out_be32((void *)GPIO0_ISR2L, 0x44000000); - out_be32((void *)GPIO0_ISR2H, 0x00000100); - out_be32((void *)GPIO0_ISR3L, 0x00000000); - out_be32((void *)GPIO0_ISR3H, 0x00000000); - - out_be32((void *)GPIO1_OR, 0x80002408); - out_be32((void *)GPIO1_TCR, 0xd6003c08); - out_be32((void *)GPIO1_OSRL, 0x0a5a0000); - out_be32((void *)GPIO1_OSRH, 0x00000000); - out_be32((void *)GPIO1_TSRL, 0x00000000); - out_be32((void *)GPIO1_TSRH, 0x00000000); - out_be32((void *)GPIO1_ISR1L, 0x00005555); - out_be32((void *)GPIO1_ISR1H, 0x40000000); - out_be32((void *)GPIO1_ISR2L, 0x04010000); - out_be32((void *)GPIO1_ISR2H, 0x00000000); - out_be32((void *)GPIO1_ISR3L, 0x01400000); - out_be32((void *)GPIO1_ISR3H, 0x00000000); - - /* patch PLB:PCI divider for 66MHz PCI */ - mfcpr(CPR0_SPCID, reg); - if (pci_is_66mhz() && (reg != 0x02000000)) { - mtcpr(CPR0_SPCID, 0x02000000); /* 133MHZ : 2 for 66MHz PCI */ - - mfcpr(CPR0_ICFG, reg); - reg |= CPR0_ICFG_RLI_MASK; - mtcpr(CPR0_ICFG, reg); - - mtspr(SPRN_DBCR0, 0x20000000); /* do chip reset */ - } - - /* - * Setup the interrupt controller polarities, triggers, etc. - */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - mtdcr(UIC0ER, 0x00000000); /* disable all */ - mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ - mtdcr(UIC0PR, 0xfffff7ef); - mtdcr(UIC0TR, 0x00000000); - mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - mtdcr(UIC1ER, 0x00000000); /* disable all */ - mtdcr(UIC1CR, 0x00000000); /* all non-critical */ - mtdcr(UIC1PR, 0xffffc7f5); - mtdcr(UIC1TR, 0x00000000); - mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - - mtdcr(UIC2SR, 0xffffffff); /* clear all */ - mtdcr(UIC2ER, 0x00000000); /* disable all */ - mtdcr(UIC2CR, 0x00000000); /* all non-critical */ - mtdcr(UIC2PR, 0x27ffffff); - mtdcr(UIC2TR, 0x00000000); - mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC2SR, 0xffffffff); /* clear all */ - - /* select Ethernet pins */ - mfsdr(SDR0_PFC1, sdr0_pfc1); - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | - SDR0_PFC1_SELECT_CONFIG_4; - mfsdr(SDR0_PFC2, sdr0_pfc2); - sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | - SDR0_PFC2_SELECT_CONFIG_4; - - /* enable 2nd IIC */ - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL; - - mtsdr(SDR0_PFC2, sdr0_pfc2); - mtsdr(SDR0_PFC1, sdr0_pfc1); - - /* setup NAND FLASH */ - mfsdr(SDR0_CUST0, sdr0_cust0); - sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL | - SDR0_CUST0_NDFC_ENABLE | - SDR0_CUST0_NDFC_BW_8_BIT | - SDR0_CUST0_NDFC_ARE_MASK | - (0x80000000 >> (28 + CONFIG_SYS_NAND_CS)); - mtsdr(SDR0_CUST0, sdr0_cust0); - - return 0; -} - -#if defined(CONFIG_MISC_INIT_F) -int misc_init_f(void) -{ - struct pci_controller hose; - hose.first_busno = 0; - hose.last_busno = 0; - hose.region_count = 0; - - if (getenv("pciearly") && (!is_monarch())) { - printf("PCI: early target init\n"); - pci_setup_indirect(&hose, PCIL0_CFGADR, PCIL0_CFGDATA); - pci_target_init(&hose); - } - return 0; -} -#endif - -/* - * misc_init_r. - */ -int misc_init_r(void) -{ - uint pbcr; - int size_val = 0; - u32 reg; - unsigned long usb2d0cr = 0; - unsigned long usb2phy0cr, usb2h0cr = 0; - unsigned long sdr0_pfc1; - unsigned long sdr0_srst0, sdr0_srst1; - char *act = getenv("usbact"); - - /* - * FLASH stuff... - */ - - /* Re-do sizing to get full correct info */ - - /* adjust flash start and offset */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; - gd->bd->bi_flashoffset = 0; - - mtdcr(EBC0_CFGADDR, PB0CR); - pbcr = mfdcr(EBC0_CFGDATA); - size_val = ffs(gd->bd->bi_flashsize) - 21; - pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); - mtdcr(EBC0_CFGADDR, PB0CR); - mtdcr(EBC0_CFGDATA, pbcr); - - /* - * Re-check to get correct base address - */ - flash_get_size(gd->bd->bi_flashstart, 0); - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - -CONFIG_SYS_MONITOR_LEN, - 0xffffffff, - &flash_info[0]); - - /* Env protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif - - /* - * USB suff... - */ - if ((act == NULL || strcmp(act, "host") == 0) && - !(in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT)) { - /* SDR Setting */ - mfsdr(SDR0_PFC1, sdr0_pfc1); - mfsdr(SDR0_USB2D0CR, usb2d0cr); - mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); - mfsdr(SDR0_USB2H0CR, usb2h0cr); - - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; - - /* - * An 8-bit/60MHz interface is the only possible alternative - * when connecting the Device to the PHY - */ - usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; - usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; - - usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; - sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; - - mtsdr(SDR0_PFC1, sdr0_pfc1); - mtsdr(SDR0_USB2D0CR, usb2d0cr); - mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); - mtsdr(SDR0_USB2H0CR, usb2h0cr); - - /* - * Take USB out of reset: - * -Initial status = all cores are in reset - * -deassert reset to OPB1, P4OPB0, OPB2, PLB42OPB1 OPB2PLB40 cores - * -wait 1 ms - * -deassert reset to PHY - * -wait 1 ms - * -deassert reset to HOST - * -wait 4 ms - * -deassert all other resets - */ - mfsdr(SDR0_SRST1, sdr0_srst1); - sdr0_srst1 &= ~(SDR0_SRST1_OPBA1 | \ - SDR0_SRST1_P4OPB0 | \ - SDR0_SRST1_OPBA2 | \ - SDR0_SRST1_PLB42OPB1 | \ - SDR0_SRST1_OPB2PLB40); - mtsdr(SDR0_SRST1, sdr0_srst1); - udelay(1000); - - mfsdr(SDR0_SRST1, sdr0_srst1); - sdr0_srst1 &= ~SDR0_SRST1_USB20PHY; - mtsdr(SDR0_SRST1, sdr0_srst1); - udelay(1000); - - mfsdr(SDR0_SRST0, sdr0_srst0); - sdr0_srst0 &= ~SDR0_SRST0_USB2H; - mtsdr(SDR0_SRST0, sdr0_srst0); - udelay(4000); - - /* finally all the other resets */ - mtsdr(SDR0_SRST1, 0x00000000); - mtsdr(SDR0_SRST0, 0x00000000); - - if (!(in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT)) { - /* enable power on USB socket */ - out_be32((void *)GPIO1_OR, - in_be32((void *)GPIO1_OR) & ~GPIO1_USB_PWR_N); - } - - printf("USB: Host\n"); - - } else if ((strcmp(act, "dev") == 0) || - (in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT)) { - mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); - - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; - mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); - - udelay (1000); - mtsdr(SDR0_SRST1, 0x672c6000); - - udelay (1000); - mtsdr(SDR0_SRST0, 0x00000080); - - udelay (1000); - mtsdr(SDR0_SRST1, 0x60206000); - - *(unsigned int *)(0xe0000350) = 0x00000001; - - udelay (1000); - mtsdr(SDR0_SRST1, 0x60306000); - - /* SDR Setting */ - mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); - mfsdr(SDR0_USB2H0CR, usb2h0cr); - mfsdr(SDR0_USB2D0CR, usb2d0cr); - mfsdr(SDR0_PFC1, sdr0_pfc1); - - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV; - - usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; - usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ; - - usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; - - sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; - sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL; - - mtsdr(SDR0_USB2H0CR, usb2h0cr); - mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); - mtsdr(SDR0_USB2D0CR, usb2d0cr); - mtsdr(SDR0_PFC1, sdr0_pfc1); - - /*clear resets*/ - udelay(1000); - mtsdr(SDR0_SRST1, 0x00000000); - udelay(1000); - mtsdr(SDR0_SRST0, 0x00000000); - - printf("USB: Device\n"); - } - - /* - * Clear PLB4A0_ACR[WRP] - * This fix will make the MAL burst disabling patch for the Linux - * EMAC driver obsolete. - */ - reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK; - mtdcr(PLB4A0_ACR, reg); - -#ifdef CONFIG_FPGA - pmc440_init_fpga(); -#endif - - /* turn off POST LED */ - out_be32((void *)GPIO1_OR, in_be32((void *)GPIO1_OR) & ~GPIO1_POST_N); - /* turn on RUN LED */ - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) & ~GPIO0_LED_RUN_N); - return 0; -} - -int is_monarch(void) -{ - if (in_be32((void *)GPIO1_IR) & GPIO1_NONMONARCH) - return 0; - - return 1; -} - -static int pci_is_66mhz(void) -{ - if (in_be32((void *)GPIO1_IR) & GPIO1_M66EN) - return 1; - return 0; -} - -static int board_revision(void) -{ - return (int)((in_be32((void *)GPIO1_IR) & GPIO1_HWID_MASK) >> 4); -} - -int checkboard(void) -{ - puts("Board: esd GmbH - PMC440"); - - gd->board_type = board_revision(); - printf(", Rev 1.%ld, ", gd->board_type); - - if (!is_monarch()) { - puts("non-"); - } - - printf("monarch, PCI=%s MHz\n", pci_is_66mhz() ? "66" : "33"); - return (0); -} - - -#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP) -/* - * Assign interrupts to PCI devices. Some OSs rely on this. - */ -void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) -{ - unsigned char int_line[] = {IRQ_PCIC, IRQ_PCID, IRQ_PCIA, IRQ_PCIB}; - - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, - int_line[PCI_DEV(dev) & 0x03]); -} -#endif - -/* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - */ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller *hose) -{ - char *ptmla_str, *ptmms_str; - - /* - * Set up Direct MMIO registers - */ - /* - * PowerPC440EPX PCI Master configuration. - * Map one 1Gig range of PLB/processor addresses to PCI memory space. - * PLB address 0x80000000-0xBFFFFFFF - * ==> PCI address 0x80000000-0xBFFFFFFF - * Use byte reversed out routines to handle endianess. - * Make this region non-prefetchable. - */ - out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */ - /* - disabled b4 setting */ - out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Addr */ - out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIL0_PMM0MA, 0xc0000001); /* 1G + No prefetching, */ - /* and enable region */ - - if (!is_monarch()) { - ptmla_str = getenv("ptm1la"); - ptmms_str = getenv("ptm1ms"); - if(NULL != ptmla_str && NULL != ptmms_str ) { - out32r(PCIL0_PTM1MS, - simple_strtoul(ptmms_str, NULL, 16)); - out32r(PCIL0_PTM1LA, - simple_strtoul(ptmla_str, NULL, 16)); - } else { - /* BAR1: default top 64MB of RAM */ - out32r(PCIL0_PTM1MS, 0xfc000001); - out32r(PCIL0_PTM1LA, 0x0c000000); - } - } else { - /* BAR1: default: complete 256MB RAM */ - out32r(PCIL0_PTM1MS, 0xf0000001); - out32r(PCIL0_PTM1LA, 0x00000000); - } - - ptmla_str = getenv("ptm2la"); /* Local Addr. Reg */ - ptmms_str = getenv("ptm2ms"); /* Memory Size/Attribute */ - if(NULL != ptmla_str && NULL != ptmms_str ) { - out32r(PCIL0_PTM2MS, simple_strtoul(ptmms_str, NULL, 16)); - out32r(PCIL0_PTM2LA, simple_strtoul(ptmla_str, NULL, 16)); - } else { - /* BAR2: default: 4MB FPGA */ - out32r(PCIL0_PTM2MS, 0xffc00001); /* Memory Size/Attribute */ - out32r(PCIL0_PTM2LA, 0xef000000); /* Local Addr. Reg */ - } - - if (is_monarch()) { - /* BAR2: map FPGA registers behind system memory at 1GB */ - pci_hose_write_config_dword(hose, 0, - PCI_BASE_ADDRESS_2, 0x40000008); - } - - /* - * Set up Configuration registers - */ - - /* Program the board's vendor id */ - pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_VENDOR_ID, - CONFIG_SYS_PCI_SUBSYS_VENDORID); - - /* disabled for PMC405 backward compatibility */ - /* Configure command register as bus master */ - /* pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); */ - - - /* 240nS PCI clock */ - pci_hose_write_config_word(hose, 0, PCI_LATENCY_TIMER, 1); - - /* No error reporting */ - pci_hose_write_config_word(hose, 0, PCI_ERREN, 0); - - if (!is_monarch()) { - /* Program the board's subsystem id/classcode */ - pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID, - CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH); - pci_hose_write_config_word(hose, 0, PCI_CLASS_SUB_CODE, - CONFIG_SYS_PCI_CLASSCODE_NONMONARCH); - - /* PCI configuration done: release ERREADY */ - out_be32((void *)GPIO1_OR, - in_be32((void *)GPIO1_OR) | GPIO1_PPC_EREADY); - out_be32((void *)GPIO1_TCR, - in_be32((void *)GPIO1_TCR) | GPIO1_PPC_EREADY); - } else { - /* Program the board's subsystem id/classcode */ - pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID, - CONFIG_SYS_PCI_SUBSYS_ID_MONARCH); - pci_hose_write_config_word(hose, 0, PCI_CLASS_SUB_CODE, - CONFIG_SYS_PCI_CLASSCODE_MONARCH); - } - - /* enable host configuration */ - pci_hose_write_config_dword(hose, 0, PCI_BRDGOPT2, 0x00000101); -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ - -/* - * Override weak default pci_master_init() - */ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) -void pci_master_init(struct pci_controller *hose) -{ - /* - * Only configure the master in monach mode - */ - if (is_monarch()) - __pci_master_init(hose); -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */ - -static void wait_for_pci_ready(void) -{ - if (!(in_be32((void *)GPIO1_IR) & GPIO1_PPC_EREADY)) { - printf("PCI: Waiting for EREADY (CTRL-C to skip) ... "); - while (1) { - if (ctrlc()) { - puts("abort\n"); - break; - } - if (in_be32((void *)GPIO1_IR) & GPIO1_PPC_EREADY) { - printf("done\n"); - break; - } - } - } -} - -/* - * Override weak is_pci_host() - * - * This routine is called to determine if a pci scan should be - * performed. With various hardware environments (especially cPCI and - * PPMC) it's insufficient to depend on the state of the arbiter enable - * bit in the strap register, or generic host/adapter assumptions. - * - * Rather than hard-code a bad assumption in the general 440 code, the - * 440 pci code requires the board to decide at runtime. - * - * Return 0 for adapter mode, non-zero for host (monarch) mode. - */ -#if defined(CONFIG_PCI) -int is_pci_host(struct pci_controller *hose) -{ - char *s = getenv("pciscan"); - if (s == NULL) - if (is_monarch()) { - wait_for_pci_ready(); - return 1; - } else - return 0; - else if (!strcmp(s, "yes")) - return 1; - - return 0; -} -#endif /* defined(CONFIG_PCI) */ - -#ifdef CONFIG_RESET_PHY_R -static int pmc440_setup_vsc8601(char *devname, int phy_addr, - unsigned short behavior, unsigned short method) -{ - /* adjust LED behavior */ - if (miiphy_write(devname, phy_addr, 0x1f, 0x0001) != 0) { - printf("Phy%d: register write access failed\n", phy_addr); - return -1; - } - - miiphy_write(devname, phy_addr, 0x11, 0x0010); - miiphy_write(devname, phy_addr, 0x11, behavior); - miiphy_write(devname, phy_addr, 0x10, method); - miiphy_write(devname, phy_addr, 0x1f, 0x0000); - - return 0; -} - -static int pmc440_setup_ksz9031(char *devname, int phy_addr) -{ - unsigned short id1, id2; - - if (miiphy_read(devname, phy_addr, 2, &id1) || - miiphy_read(devname, phy_addr, 3, &id2)) { - printf("Phy%d: cannot read id\n", phy_addr); - return -1; - } - - if ((id1 != 0x0022) || ((id2 & 0xfff0) != 0x1620)) { - printf("Phy%d: unexpected id\n", phy_addr); - return -1; - } - - /* MMD 2.08: adjust tx_clk pad skew */ - miiphy_write(devname, phy_addr, 0x0d, 2); - miiphy_write(devname, phy_addr, 0x0e, 8); - miiphy_write(devname, phy_addr, 0x0d, 0x4002); - miiphy_write(devname, phy_addr, 0x0e, 0xf | (0x17 << 5)); - - return 0; -} - -void reset_phy(void) -{ - char *s; - unsigned short val_method, val_behavior; - - if (gd->board_type < 4) { - /* special LED setup for NGCC/CANDES */ - s = getenv("bd_type"); - if (s && ((!strcmp(s, "ngcc")) || (!strcmp(s, "candes")))) { - val_method = 0x0e0a; - val_behavior = 0x0cf2; - } else { - /* PMC440 standard type */ - val_method = 0x0e10; - val_behavior = 0x0cf0; - } - - /* boards up to rev. 1.3 use Vitesse VSC8601 phys */ - pmc440_setup_vsc8601("ppc_4xx_eth0", CONFIG_PHY_ADDR, - val_method, val_behavior); - pmc440_setup_vsc8601("ppc_4xx_eth1", CONFIG_PHY1_ADDR, - val_method, val_behavior); - } else { - /* rev. 1.4 uses a Micrel KSZ9031 */ - pmc440_setup_ksz9031("ppc_4xx_eth0", CONFIG_PHY_ADDR); - pmc440_setup_ksz9031("ppc_4xx_eth1", CONFIG_PHY1_ADDR); - } -} -#endif - -#if defined(CONFIG_SYS_EEPROM_WREN) -/* - * Input: <dev_addr> I2C address of EEPROM device to enable. - * <state> -1: deliver current state - * 0: disable write - * 1: enable write - * Returns: -1: wrong device address - * 0: dis-/en- able done - * 0/1: current state if <state> was -1. - */ -int eeprom_write_enable(unsigned dev_addr, int state) -{ - if ((CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) && - (CONFIG_SYS_I2C_BOOT_EEPROM_ADDR != dev_addr)) { - return -1; - } else { - switch (state) { - case 1: - /* Enable write access, clear bit GPIO_SINT2. */ - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) & ~GPIO0_EP_EEP); - state = 0; - break; - case 0: - /* Disable write access, set bit GPIO_SINT2. */ - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) | GPIO0_EP_EEP); - state = 0; - break; - default: - /* Read current status back. */ - state = (0 == (in_be32((void *)GPIO0_OR) - & GPIO0_EP_EEP)); - break; - } - } - return state; -} -#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ - -#define CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS 3 -int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset, - uchar *buffer, unsigned cnt) -{ - unsigned end = offset + cnt; - unsigned blk_off; - int rcode = 0; - -#if defined(CONFIG_SYS_EEPROM_WREN) - eeprom_write_enable(dev_addr, 1); -#endif - /* - * Write data until done or would cross a write page boundary. - * We must write the address again when changing pages - * because the address counter only increments within a page. - */ - while (offset < end) { - unsigned alen, len; - unsigned maxlen; - uchar addr[2]; - - blk_off = offset & 0xFF; /* block offset */ - - addr[0] = offset >> 8; /* block number */ - addr[1] = blk_off; /* block offset */ - alen = 2; - addr[0] |= dev_addr; /* insert device address */ - - len = end - offset; - -#define BOOT_EEPROM_PAGE_SIZE (1 << CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS) -#define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1)) - - maxlen = BOOT_EEPROM_PAGE_SIZE - - BOOT_EEPROM_PAGE_OFFSET(blk_off); - if (maxlen > I2C_RXTX_LEN) - maxlen = I2C_RXTX_LEN; - - if (len > maxlen) - len = maxlen; - - if (i2c_write (addr[0], offset, alen-1, buffer, len) != 0) - rcode = 1; - - buffer += len; - offset += len; - -#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS) - udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000); -#endif - } -#if defined(CONFIG_SYS_EEPROM_WREN) - eeprom_write_enable(dev_addr, 0); -#endif - return rcode; -} - -static int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset, - uchar *buffer, unsigned cnt) -{ - unsigned end = offset + cnt; - unsigned blk_off; - int rcode = 0; - - /* - * Read data until done or would cross a page boundary. - * We must write the address again when changing pages - * because the next page may be in a different device. - */ - while (offset < end) { - unsigned alen, len; - unsigned maxlen; - uchar addr[2]; - - blk_off = offset & 0xFF; /* block offset */ - - addr[0] = offset >> 8; /* block number */ - addr[1] = blk_off; /* block offset */ - alen = 2; - - addr[0] |= dev_addr; /* insert device address */ - - len = end - offset; - - maxlen = 0x100 - blk_off; - if (maxlen > I2C_RXTX_LEN) - maxlen = I2C_RXTX_LEN; - if (len > maxlen) - len = maxlen; - - if (i2c_read (addr[0], offset, alen-1, buffer, len) != 0) - rcode = 1; - buffer += len; - offset += len; - } - - return rcode; -} - -#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) -int board_usb_init(int index, enum usb_init_type init) -{ - char *act = getenv("usbact"); - int i; - - if ((act == NULL || strcmp(act, "host") == 0) && - !(in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT)) - /* enable power on USB socket */ - out_be32((void *)GPIO1_OR, - in_be32((void *)GPIO1_OR) & ~GPIO1_USB_PWR_N); - - for (i=0; i<1000; i++) - udelay(1000); - - return 0; -} - -int usb_board_stop(void) -{ - /* disable power on USB socket */ - out_be32((void *)GPIO1_OR, in_be32((void *)GPIO1_OR) | GPIO1_USB_PWR_N); - return 0; -} - -int board_usb_cleanup(int index, enum usb_init_type init) -{ - return usb_board_stop(); -} -#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */ - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, bd_t *bd) -{ - int rc; - - __ft_board_setup(blob, bd); - - /* - * Disable PCI in non-monarch mode. - */ - if (!is_monarch()) { - rc = fdt_find_and_setprop(blob, "/plb/pci@1ec000000", "status", - "disabled", sizeof("disabled"), 1); - if (rc) { - printf("Unable to update property status in PCI node, "); - printf("err=%s\n", fdt_strerror(rc)); - } - } - - return 0; -} -#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/esd/pmc440/pmc440.h b/board/esd/pmc440/pmc440.h deleted file mode 100644 index 84e0b1f..0000000 --- a/board/esd/pmc440/pmc440.h +++ /dev/null @@ -1,135 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __PMC440_H__ -#define __PMC440_H__ - -/* - * GPIOs - */ -#define GPIO1_INTA_FAKE (0x80000000 >> (45-32)) /* GPIO45 OD */ -#define GPIO1_NONMONARCH (0x80000000 >> (63-32)) /* GPIO63 I */ -#define GPIO1_PPC_EREADY (0x80000000 >> (62-32)) /* GPIO62 I/O */ -#define GPIO1_M66EN (0x80000000 >> (61-32)) /* GPIO61 I */ -#define GPIO1_POST_N (0x80000000 >> (60-32)) /* GPIO60 O */ -#define GPIO1_IOEN_N (0x80000000 >> (50-32)) /* GPIO50 O */ -#define GPIO1_HWID_MASK (0xf0000000 >> (56-32)) /* GPIO56..59 I */ - -#define GPIO1_USB_PWR_N (0x80000000 >> (32-32)) /* GPIO32 I */ -#define GPIO0_LED_RUN_N (0x80000000 >> 30) /* GPIO30 O */ -#define GPIO0_EP_EEP (0x80000000 >> 23) /* GPIO23 O */ -#define GPIO0_USB_ID (0x80000000 >> 21) /* GPIO21 I */ -#define GPIO0_USB_PRSNT (0x80000000 >> 20) /* GPIO20 I */ - -/* - * FPGA programming pin configuration - */ -#define GPIO1_FPGA_PRG (0x80000000 >> (53-32)) /* FPGA program pin (ppc output) */ -#define GPIO1_FPGA_CLK (0x80000000 >> (51-32)) /* FPGA clk pin (ppc output) */ -#define GPIO1_FPGA_DATA (0x80000000 >> (52-32)) /* FPGA data pin (ppc output) */ -#define GPIO1_FPGA_DONE (0x80000000 >> (55-32)) /* FPGA done pin (ppc input) */ -#define GPIO1_FPGA_INIT (0x80000000 >> (54-32)) /* FPGA init pin (ppc input) */ -#define GPIO0_FPGA_FORCEINIT (0x80000000 >> 27) /* low: force INIT# low */ - -/* - * FPGA interface - */ -#define FPGA_BA CONFIG_SYS_FPGA_BASE0 -#define FPGA_OUT32(p,v) out_be32(((void*)(p)), (v)) -#define FPGA_IN32(p) in_be32((void*)(p)) -#define FPGA_SETBITS(p,v) out_be32(((void*)(p)), in_be32((void*)(p)) | (v)) -#define FPGA_CLRBITS(p,v) out_be32(((void*)(p)), in_be32((void*)(p)) & ~(v)) - -struct pmc440_fifo_s { - u32 data; - u32 ctrl; -}; - -/* fifo ctrl register */ -#define FIFO_IE (1 << 15) -#define FIFO_OVERFLOW (1 << 10) -#define FIFO_EMPTY (1 << 9) -#define FIFO_FULL (1 << 8) -#define FIFO_LEVEL_MASK 0x000000ff - -#define FIFO_COUNT 4 - -struct pmc440_fpga_s { - u32 ctrla; - u32 status; - u32 ctrlb; - u32 pad1[0x40 / sizeof(u32) - 3]; - u32 irig_time; /* offset: 0x0040 */ - u32 irig_tod; - u32 irig_cf; - u32 pad2; - u32 irig_rx_time; /* offset: 0x0050 */ - u32 pad3[3]; - u32 hostctrl; /* offset: 0x0060 */ - u32 pad4[0x20 / sizeof(u32) - 1]; - struct pmc440_fifo_s fifo[FIFO_COUNT]; /* 0x0080..0x009f */ -}; - -typedef struct pmc440_fpga_s pmc440_fpga_t; - -/* ctrl register */ -#define CTRL_HOST_IE (1 << 8) - -/* outputs */ -#define RESET_EN (1 << 31) -#define CLOCK_EN (1 << 30) -#define RESET_OUT (1 << 19) -#define CLOCK_OUT (1 << 22) -#define RESET_OUT (1 << 19) -#define IRIGB_R_OUT (1 << 14) - -/* status register */ -#define STATUS_VERSION_SHIFT 24 -#define STATUS_VERSION_MASK 0xff000000 -#define STATUS_HWREV_SHIFT 20 -#define STATUS_HWREV_MASK 0x00f00000 - -#define STATUS_CAN_ISF (1 << 11) -#define STATUS_CSTM_ISF (1 << 10) -#define STATUS_FIFO_ISF (1 << 9) -#define STATUS_HOST_ISF (1 << 8) - -/* inputs */ -#define RESET_IN (1 << 0) -#define CLOCK_IN (1 << 1) -#define IRIGB_R_IN (1 << 5) - -/* hostctrl register */ -#define HOSTCTRL_PMCRSTOUT_GATE (1 << 17) -#define HOSTCTRL_PMCRSTOUT_FLAG (1 << 16) -#define HOSTCTRL_CSTM1IE_GATE (1 << 7) -#define HOSTCTRL_CSTM1IW_FLAG (1 << 6) -#define HOSTCTRL_CSTM0IE_GATE (1 << 5) -#define HOSTCTRL_CSTM0IW_FLAG (1 << 4) -#define HOSTCTRL_FIFOIE_GATE (1 << 3) -#define HOSTCTRL_FIFOIE_FLAG (1 << 2) -#define HOSTCTRL_HCINT_GATE (1 << 1) -#define HOSTCTRL_HCINT_FLAG (1 << 0) - -#define NGCC_CTRL_BASE (CONFIG_SYS_FPGA_BASE0 + 0x80000) -#define NGCC_CTRL_FPGARST_N (1 << 2) - -/* - * FPGA to PPC interrupt - */ -#define IRQ0_FPGA (32+28) /* UIC1 - FPGA internal */ -#define IRQ1_FPGA (32+30) /* UIC1 - custom module */ -#define IRQ2_FPGA (64+ 3) /* UIC2 - custom module / CAN */ -#define IRQ_ETH0 (64+ 4) /* UIC2 */ -#define IRQ_ETH1 ( 27) /* UIC0 */ -#define IRQ_RTC (64+ 0) /* UIC2 */ -#define IRQ_PCIA (64+ 1) /* UIC2 */ -#define IRQ_PCIB (32+18) /* UIC1 */ -#define IRQ_PCIC (32+19) /* UIC1 */ -#define IRQ_PCID (32+20) /* UIC1 */ - -#endif /* __PMC440_H__ */ diff --git a/board/esd/pmc440/sdram.c b/board/esd/pmc440/sdram.c deleted file mode 100644 index c379e77..0000000 --- a/board/esd/pmc440/sdram.c +++ /dev/null @@ -1,140 +0,0 @@ -/* - * (C) Copyright 2009 - * Matthias Fuchs, esd gmbh, matthias.fuchs@esd.eu - * - * (C) Copyright 2006 - * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com - * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com - * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com - * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com - * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com - * - * (C) Copyright 2006-2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* define DEBUG for debug output */ -#undef DEBUG - -#include <common.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/mmu.h> -#include <asm/ppc440.h> - -DECLARE_GLOBAL_DATA_PTR; - -extern int denali_wait_for_dlllock(void); -extern void denali_core_search_data_eye(void); - -struct sdram_conf_s { - ulong size; - int rows; - int banks; -}; - -struct sdram_conf_s sdram_conf[] = { - {(1024 << 20), 14, 8}, /* 1GByte: 4x2GBit, 14x10, 8 banks */ - {(512 << 20), 13, 8}, /* 512MByte: 4x1GBit, 13x10, 8 banks */ - {(256 << 20), 13, 4}, /* 256MByte: 4x512MBit, 13x10, 4 banks */ -}; - -/* - * dram_init -- 440EPx's DDR controller is a DENALI Core - */ -int initdram_by_rb(int rows, int banks) -{ - ulong speed = get_bus_freq(0); - - mtsdram(DDR0_02, 0x00000000); - - mtsdram(DDR0_00, 0x0000190A); - mtsdram(DDR0_01, 0x01000000); - mtsdram(DDR0_03, 0x02030602); - mtsdram(DDR0_04, 0x0A020200); - mtsdram(DDR0_05, 0x02020308); - mtsdram(DDR0_06, 0x0102C812); - mtsdram(DDR0_07, 0x000D0100); - mtsdram(DDR0_08, 0x02430001); - mtsdram(DDR0_09, 0x00011D5F); - mtsdram(DDR0_10, 0x00000100); - mtsdram(DDR0_11, 0x0027C800); - mtsdram(DDR0_12, 0x00000003); - mtsdram(DDR0_14, 0x00000000); - mtsdram(DDR0_17, 0x19000000); - mtsdram(DDR0_18, 0x19191919); - mtsdram(DDR0_19, 0x19191919); - mtsdram(DDR0_20, 0x0B0B0B0B); - mtsdram(DDR0_21, 0x0B0B0B0B); - mtsdram(DDR0_22, 0x00267F0B); - mtsdram(DDR0_23, 0x00000000); - mtsdram(DDR0_24, 0x01010002); - if (speed > 133333334) - mtsdram(DDR0_26, 0x5B26050C); - else - mtsdram(DDR0_26, 0x5B260408); - mtsdram(DDR0_27, 0x0000682B); - mtsdram(DDR0_28, 0x00000000); - mtsdram(DDR0_31, 0x00000000); - - mtsdram(DDR0_42, - DDR0_42_ADDR_PINS_DECODE(14 - rows) | - 0x00000006); - mtsdram(DDR0_43, - DDR0_43_EIGHT_BANK_MODE_ENCODE(8 == banks ? 1 : 0) | - 0x030A0200); - - mtsdram(DDR0_44, 0x00000003); - mtsdram(DDR0_02, 0x00000001); - - denali_wait_for_dlllock(); - -#ifdef CONFIG_DDR_DATA_EYE - /* - * Perform data eye search if requested. - */ - denali_core_search_data_eye(); -#endif - /* - * Clear possible errors resulting from data-eye-search. - * If not done, then we could get an interrupt later on when - * exceptions are enabled. - */ - set_mcsr(get_mcsr()); - - return 0; -} - -int dram_init(void) -{ - phys_size_t size; - int n; - - /* go through supported memory configurations */ - for (n = 0; n < ARRAY_SIZE(sdram_conf); n++) { - size = sdram_conf[n].size; - - /* program TLB entries */ - program_tlb(0, CONFIG_SYS_SDRAM_BASE, size, - TLB_WORD2_I_ENABLE); - - /* - * setup denali core - */ - initdram_by_rb(sdram_conf[n].rows, - sdram_conf[n].banks); - - /* check for suitable configuration */ - if (get_ram_size(CONFIG_SYS_SDRAM_BASE, size) == size) { - gd->ram_size = size; - return 0; - } - - /* delete TLB entries */ - remove_tlb(CONFIG_SYS_SDRAM_BASE, size); - } - - return -ENXIO; -} diff --git a/board/esd/vom405/Kconfig b/board/esd/vom405/Kconfig deleted file mode 100644 index ecdf8c9..0000000 --- a/board/esd/vom405/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_VOM405 - -config SYS_BOARD - default "vom405" - -config SYS_VENDOR - default "esd" - -config SYS_CONFIG_NAME - default "VOM405" - -endif diff --git a/board/esd/vom405/MAINTAINERS b/board/esd/vom405/MAINTAINERS deleted file mode 100644 index 385f60a..0000000 --- a/board/esd/vom405/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -VOM405 BOARD -M: Matthias Fuchs <matthias.fuchs@esd-electronics.com> -S: Maintained -F: board/esd/vom405/ -F: include/configs/VOM405.h -F: configs/VOM405_defconfig diff --git a/board/esd/vom405/Makefile b/board/esd/vom405/Makefile deleted file mode 100644 index 7cf5c02..0000000 --- a/board/esd/vom405/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# Objects for Xilinx JTAG programming (CPLD) -CPLD = ../common/xilinx_jtag/lenval.o \ - ../common/xilinx_jtag/micro.o \ - ../common/xilinx_jtag/ports.o - -obj-y = vom405.o flash.o ../common/misc.o $(CPLD) diff --git a/board/esd/vom405/flash.c b/board/esd/vom405/flash.c deleted file mode 100644 index 23e8164..0000000 --- a/board/esd/vom405/flash.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - uint pbcr; - unsigned long base_b0; - int size_val = 0; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0<<20); - } - - /* Setup offsets */ - flash_get_offsets (-size_b0, &flash_info[0]); - - /* Re-do sizing to get full correct info */ - mtdcr(EBC0_CFGADDR, PB0CR); - pbcr = mfdcr(EBC0_CFGDATA); - mtdcr(EBC0_CFGADDR, PB0CR); - base_b0 = -size_b0; - switch (size_b0) { - case 1 << 20: - size_val = 0; - break; - case 2 << 20: - size_val = 1; - break; - case 4 << 20: - size_val = 2; - break; - case 8 << 20: - size_val = 3; - break; - case 16 << 20: - size_val = 4; - break; - } - pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); - mtdcr(EBC0_CFGDATA, pbcr); - - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - -CONFIG_SYS_MONITOR_LEN, - 0xffffffff, - &flash_info[0]); - - flash_info[0].size = size_b0; - - return (size_b0); -} diff --git a/board/esd/vom405/vom405.c b/board/esd/vom405/vom405.c deleted file mode 100644 index 7de6f66..0000000 --- a/board/esd/vom405/vom405.c +++ /dev/null @@ -1,148 +0,0 @@ -/* - * (C) Copyright 2001-2004 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <command.h> -#include <malloc.h> -#include <sja1000.h> - -DECLARE_GLOBAL_DATA_PTR; - -extern void lxt971_no_sleep(void); - -/* - * generate a short spike on the CAN tx line - * to bring the couplers in sync - */ -void init_coupler(u32 addr) -{ - struct sja1000_basic_s *ctrl = (struct sja1000_basic_s *)addr; - - /* reset */ - out_8(&ctrl->cr, CR_RR); - - /* dominant */ - out_8(&ctrl->btr0, 0x00); /* btr setup is required */ - out_8(&ctrl->btr1, 0x14); /* we use 1Mbit/s */ - out_8(&ctrl->oc, OC_TP1 | OC_TN1 | OC_POL1 | - OC_TP0 | OC_TN0 | OC_POL0 | OC_MODE1); - out_8(&ctrl->cr, 0x00); - - /* delay */ - in_8(&ctrl->cr); - in_8(&ctrl->cr); - in_8(&ctrl->cr); - in_8(&ctrl->cr); - - /* reset */ - out_8(&ctrl->cr, CR_RR); -} - -int board_early_init_f (void) -{ - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive - * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive - * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive - * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive - * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive - */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ - mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */ - mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - /* - * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us - */ - mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ - - /* - * Reset CPLD via GPIO12 (CS3) pin - */ - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) & ~(0x80000000 >> 12)); - udelay(1000); /* wait 1ms */ - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) | (0x80000000 >> 12)); - udelay(1000); /* wait 1ms */ - - return 0; -} - -int misc_init_r (void) -{ - /* adjust flash start and offset */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; - gd->bd->bi_flashoffset = 0; - - /* - * Init magnetic coupler - */ - if (!getenv("noinitcoupler")) - init_coupler(CAN_BA); - - return (0); -} - -/* - * Check Board Identity: - */ -int checkboard (void) -{ - char str[64]; - int i = getenv_f("serial#", str, sizeof(str)); - int flashcnt; - int delay; - u8 *led_reg = (u8 *)(CAN_BA + 0x1000); - - puts ("Board: "); - - if (i == -1) { - puts ("### No HW ID - assuming VOM405"); - } else { - puts(str); - } - - printf(" (PLD-Version=%02d)\n", in_8(led_reg)); - - /* - * Flash LEDs - */ - for (flashcnt = 0; flashcnt < 3; flashcnt++) { - out_8(led_reg, 0x40); /* LED_B..D off */ - for (delay = 0; delay < 100; delay++) - udelay(1000); - out_8(led_reg, 0x47); /* LED_B..D on */ - for (delay = 0; delay < 50; delay++) - udelay(1000); - } - out_8(led_reg, 0x40); - - return 0; -} - -void reset_phy(void) -{ -#ifdef CONFIG_LXT971_NO_SLEEP - - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); -#endif -} |