Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

* 'master' of git://git.denx.de/u-boot-mpc85xx:
  powerpc/mpc85xx: Fix Handling the lack of L2 cache on P2040/P2040E
  powerpc/mpc85xx: Workaround for erratum CPU_A011
  powerpc/mpc85xx: Ignore E bit for SVR_SOC_VER()
  powerpc/P4080: Check SVR for CPU22 workaround
  lib/powerpc: addrmap_phys_to_virt() should return a pointer
  powerpc/85xx: clean up P1022DS board configuration header file
  powerpc/85xx: fdt_set_phy_handle() should return an error code
  powerpc/85xx: minor clean-ups to the P2020DS board header file
  powerpc/p1010rdb: add readme document for p1010rdb
  powerpc/mpc85xx:NAND_SPL:Avoid IFC/eLBC Base address setting
  powerpc/mpc85xx:Add debugger support for e500v2 SoC
  powerpc/85xx:Fix NAND code base to support debugger
  powerpc/85xx:Make debug exception vector accessible
  powerpc/85xx:Fix MSR[DE] bit in MSR to support debugger
  PATCH 1/4][v4] doc:Add documentation for e500 external debugger support
  powerpc/p1010rdb: update mux config of p1010rdb board
  powerpc/mpc85xx:Add BSC9131 RDB Support
  powerpc/mpc85xx:Add BSC9131/BSC9130/BSC9231 Processor Support
  powerpc/85xx: Add USB device-tree fixup for various platforms

Signed-off-by: Wolfgang Denk <wd@denx.de>

1 files changed, 83 insertions, 0 deletions

diff --git a/board/freescale/bsc9131rdb/bsc9131rdb.c b/board/freescale/bsc9131rdb/bsc9131rdb.c
new file mode 100644
index 0000000..2e0e55f
--- /dev/null
+++ b/board/freescale/bsc9131rdb/bsc9131rdb.c
@@ -0,0 +1,83 @@
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <fsl_mdio.h>
+#include <tsec.h>
+#include <netdev.h>
+
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+	clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42);
+	setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS);
+
+	clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43);
+	setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK |
+			MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD);
+	setbits_be32(&gur->halt_req_mask, HALTED_TO_HALT_REQ_MASK_0);
+	clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_IFC_AD_GPIO_MASK |
+			MPC85xx_PMUXCR_IFC_AD17_GPO_MASK,
+			MPC85xx_PMUXCR_IFC_AD_GPIO |
+			MPC85xx_PMUXCR_IFC_AD17_GPO | MPC85xx_PMUXCR_SDHC_USIM);
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	struct cpu_type *cpu;
+
+	cpu = gd->cpu;
+	printf("Board: %sRDB\n", cpu->name);
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+
+	ft_cpu_setup(blob, bd);
+
+	base = getenv_bootm_low();
+	size = getenv_bootm_size();
+
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+	fdt_fixup_dr_usb(blob, bd);
+}
+#endif